參數資料
型號: MC10E212FN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 3-BIT SCANNABLE REGISTERED ADDRESS DRIVER
中文描述: 10E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28
封裝: PLASTIC, LCC-28
文件頁數: 1/4頁
文件大?。?/td> 111K
代理商: MC10E212FN
LOGIC DIAGRAM
25
24
23
22
21
20
19
18
17
16
15
14
13
12
5
6
7
8
9
10
11
26
27
28
2
3
4
SHIFT MR
NC S-OUTVCCOQ2b
Q2a
Q2b
Q2a
VCC
Q1b
Q1a
Q1b
Q1a
NC VCCOQ0a
LOAD
CLK
D2
VEE
D1
D0
S-IN
Q0b
Q0a
Q0b VCCO
D2
D1
D0
S-IN
LOAD
SHIFT
CLK
MR
D
Q
D
D
Q
Q
S-OUT
Q2b
Q2a
Q2b
Q2a
Q1b
Q1a
Q1b
Q1a
Q0b
Q0a
Q0b
Q0a
1
Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E212 is a scannable registered ECL driver typically
used as a fan-out memory address driver for ECL cache driving. In a VLSI
array based CPU design, use of the E212 allows the user to conserve
array output cell functionality and also output pins.
The input shift register is designed with control logic which greatly
facilitates its use in boundary scan applications.
Scannable Version E112 Driver
1025ps Max. CLK to Output
Dual Differential Outputs
Master Reset
Extended 100E VEE Range of – 4.2V to – 5.46V
Internal 75k
Input Pulldown Resistors
PIN NAMES
Pin
Function
D0– D2
S-IN
LOAD
SHIFT
CLK
MR
S-OUT
Q[0:2]a, Q[0:2]b
Q[0:2]a, Q[0:2]b
Data Inputs
Scan Input
LOAD/HOLD Control
Scan Control
Clock
Reset
Scan Output
True Outputs
Inverting Outputs
3-BIT SCANNABLE
REGISTERED
ADDRESS DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
相關PDF資料
PDF描述
MC100E241FN 8-BIT SCANNABLE REGISTER
MC10E241 0.345A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC 0 to 85
MC10E241FN 0.345A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC 0 to 85
MC100E256FN 3-BIT 4:1 MUX-LATCH
MC10E256 Replaced by TPS2056A : 0.345A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC -40 to 85
相關代理商/技術參數
參數描述
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