參數(shù)資料
型號(hào): MC100E256FN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 3-BIT 4:1 MUX-LATCH
中文描述: 100E SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC28
封裝: PLASTIC, LCC-28
文件頁(yè)數(shù): 1/5頁(yè)
文件大?。?/td> 110K
代理商: MC100E256FN
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E256 contains three 4:1 multiplexers followed by
transparent latches with differential outputs. Separate Select controls are
provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and
output data is controlled by the multiplexer select controls. A logic HIGH
on LEN latches the outputs. The Master Reset (MR) overrides all other
controls to set the Q outputs LOW.
950ps Max. D to Output
850ps Max. LEN to Output
Split Select
Differential Outputs
Extended 100E VEE Range of – 4.2V to – 5.46V
75k
Input Pulldown Resistors
SEL1A
SEL1B
SEL2
VEE
LEN
MR
D1c
26
27
28
2
3
4
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
5
6
7
8
9
10
D1b
D1a
D2d
D2c
D2b
D2a
VCCO
Q2
Q2
VCC
Q1
Q1
VCCO
Q0
D1d
D0a
D0b
D0c
D0d
VCCO
Q0
1
Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
FUNCTION TABLE
Pin
State
Operation
SEL2
SEL1A
SEL1B
H
H
H
Output c/d Data
Input d Data
Input b Data
PIN NAMES
Pin
Function
D0x– D2x
SEL1A, SEL1B
SEL2
LEN
MR
Q0, Q0– Q2, Q2
Data Inputs
First-stage Select Inputs
Second-stage Select input
Latch Enable
Master Reset
Data Outputs
3-BIT 4:1
MUX-LATCH
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
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