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參數(shù)資料
| 型號(hào)： | MC10E1652L |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 0K |
| 描述： | IC COMPARATOR DUAL ECL 16-CDIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | MOSAIC III™ |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 2 |
| 輸出類型： | 差分，ECL |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 100mA |
| 電流 - 靜態(tài)（最大值）： | 50mA |
| 磁滯： | 27mV |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 16-CDIP（0.300"，7.62mm） |
| 安裝類型： | 通孔 |
| 包裝： | 管件 |
MC10E1652
http://onsemi.com
5
APPLICATIONS INFORMATION
The timing diagram (Figure 5.) is presented to illustrate
the MC10E1652’s compare and latch features. When the
signal on the LEN pin is at a logic high level, the device is
operating in the “compare mode,” and the signal on the input
arrives at the output after a nominal propagation delay (tPHL,
tPLH). The input signal must be asserted for a time, ts, prior
to the negative going transition on LEN and held for a time,
th, after the LEN transition. After time th, the latch is
operating in the “l(fā)atch mode,” thus transitions on the input
do not appear at the output. The device continues to operate
in the “l(fā)atch mode” until the latch is asserted once again.
Moreover, the LEN pulse must meet the minimum pulse
width (tpw) requirement to effect the correct input-output
relationship. Note that the LEN waveform in Figure 5.
shows the LEN signal swinging around a reference labeled
VBBINT; this waveform emphasizes the requirement that
LEN follow typical ECL 10KH logic levels because
VBBINT is the internally generated reference level, hence is
nominally at the ECL VBB level.
Finally, VOD is the input voltage overdrive and represents
the voltage level beyond the threshold level (VTHR) to which
the input is driven. As an example, if the threshold level is
set on one of the comparator inputs as 80 mV and the input
signal swing on the complementary input is from zero to 100
mV, the positive going overdrive would be 20 mV and the
negative going overdrive would be 80 mV. The result of
differing overdrive levels is that the devices have shorter
propagation delays with greater overdrive because the
threshold level is crossed sooner than the case of lower
overdrive levels. Typically, semiconductor manufactures
refer to the threshold voltage as the input offset voltage
(VOS) since the threshold voltage is the sum of the
externally supplied reference voltage and inherent device
offset voltage.
Figure 5. Input/Output Timing Diagram
Q
VTHR
V
LEN
VBBINT
VOD
tpw
th
ts
tPHL
tPLH(LEN)
VIN
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