- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26792 > MC10131L (ON SEMICONDUCTOR) 10K SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 PDF資料下載
參數(shù)資料
| 型號： | MC10131L |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 10K SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 109K |
| 代理商： | MC10131L |
Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10131/D
MC10131
Dual Type D Master-Slave
Flip-Flop
The MC10131 is a dual master–slave type D flip–flop.
Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flip–flop may be clocked separately by
holding the common clock in the low state and using the enable inputs
for the clocking function. If the common clock is to be used to clock
the flip–flop, the Clock Enable inputs must be in the low state. In this
case, the enable inputs perform the function of controlling the
common clock.
The output states of the flip–flop change on the positive transition of
the clock. A change in the information present at the data (D) input
will not affect the output information at any other time due to master
slave construction.
P
D = 235 mW typ/pkg (No Load)
F
Tog = 160 MHz typ
t
pd = 3.0 ns typ
t
r, tf = 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
S1 5
D1 7
CE1 6
R1 4
CC 9
R2 13
CE2 11
D2 10
S2 12
Q1
Q2
2
3
14
15
DIP PIN ASSIGNMENT
VCC1
Q1
R1
S1
CE1
D1
VEE
VCC2
Q2
R2
S2
CE2
D2
CC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10131L
CDIP–16
25 Units / Rail
MC10131P
PDIP–16
25 Units / Rail
MC10131FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10131L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10131
AWLYYWW
1
16
MC10131P
AWLYYWW
CD
Qn+1
CLOCKED TRUTH TABLE
LX
Qn
HL
L
HH
H
C = CE + CC.A clock H is a clock transition from a low to a
high state.
RS
Qn+1
R–S TRUTH TABLE
LH
H
HL
L
H
N.D.
N.D. = Not Defined
LL
Qn
相關PDF資料 |
PDF描述 |
|---|---|
| MC10133L | 10K SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16 |
| MC10133FN | 10K SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PQCC20 |
| MC10135FNR2 | 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20 |
| MC10135P | 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| MC10135FN | 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC10131P | 制造商:ON Semiconductor 功能描述:Flip Flop D-Master-Slave Type Pos-Edge 1-Element 16-Pin PDIP Rail |
| MC10133L | 制造商:ON Semiconductor 功能描述: |
| MC10133LD | 制造商:Motorola Inc 功能描述:Latch, Dual, 2 Bit, 16 Pin, Ceramic, DIP |
| MC10134P | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10135FN | 制造商:ON Semiconductor 功能描述:Flip Flop JK-Master-Slave Type Pos-Edge 1-Element 20-Pin PLLC Rail 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。