參數(shù)資料
型號(hào): MC10111P
廠商: ON SEMICONDUCTOR
元件分類: 門(mén)電路
英文描述: 10K SERIES, DUAL 3-INPUT NOR GATE, PDIP16
封裝: PLASTIC, DIP-16
文件頁(yè)數(shù): 1/5頁(yè)
文件大?。?/td> 156K
代理商: MC10111P
Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 8
1
Publication Order Number:
MC10111/D
MC10111
Dual 3Input/3Ouput NOR
Gate
The MC10111 is designed to drive up to three transmission lines
simul taneously. The multiple outputs of this device also allow the
wire “OR”ing of several levels of gating for minimization of gate and
package count.
The ability to control three parallel lines from a single point makes
the MC10111 particularly useful in clock distribution applications
where minimum clock skew is desired. Three VCC pins are provided
and each one should be used.
PD = 80 mW typ/gate (No Load)
tpd = 2.4 ns typ (All Outputs Loaded)
tr, tf = 2.2 ns typ (20%80%)
DIP
PIN ASSIGNMENT
VCC1
AOUT
AIN
VEE
VCC2
VCC1
BOUT
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for DualinLine Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
LOGIC DIAGRAM
VCC1 = PIN 1,15
VCC2 = PIN 16
VEE = PIN 8
12
11
10
9
13
14
2
7
6
5
3
4
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10111L
CDIP16
25 Units / Rail
MC10111P
PDIP16
25 Units / Rail
MC10111FN
PLCC20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP16
L SUFFIX
CASE 620
MC10111L
AWLYYWW
PDIP16
P SUFFIX
CASE 648
PLCC20
FN SUFFIX
CASE 775
10111
AWLYYWW
1
16
MC10111P
AWLYYWW
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