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參數(shù)資料
| 型號： | MC100LVEP34DTR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip |
| 中文描述： | 100LVE SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 164K |
| 代理商： | MC100LVEP34DTR2G |
MC100LVEP34
http://onsemi.com
2
V
CC
Q0
Q1
V
CC
Q2
15
16
14
13
12
11
10
2
1
3
4
5
6
7
V
CC
9
8
EN
NC
CLK
CLK
V
BB
MR
V
EE
D
Q
R
Q
R
÷
2
Q
R
÷
4
Q
R
÷
8
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Q0
Q1
Q2
Figure 1. 16
Lead Pinout
(Top View)
and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Function
CLK*, CLK**
ECL Diff Clock Inputs
EN*
ECL Sync Enable
MR*
ECL Master Reset
Q0, Q0
ECL Diff
÷
2 Outputs
Q1, Q1
ECL Diff
÷
4 Outputs
Q2, Q2
ECL Diff
÷
8 Outputs
V
BB
Reference Voltage Output
V
CC
Positive Supply
V
EE
Negative Supply
NC
No Connect
* Pins will default LOW when left open.
**Pins will default to V
CC
/2 when left open.
Table 2. FUNCTION TABLE
CLK
EN
MR
FUNCTION
Z
ZZ
X
L
H
X
L
L
H
Divide
Hold Q
0
3
Reset Q
0
3
Z = Low
to
High Transition
ZZ = High
to
Low Transition
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