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參數(shù)資料
| 型號(hào)： | MC100LVEP34DTR2G |
| 廠(chǎng)商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip |
| 中文描述： | 100LVE SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | LEAD FREE, TSSOP-16 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 164K |
| 代理商： | MC100LVEP34DTR2G |
Semiconductor Components Industries, LLC, 2005
February, 2005
Rev. 7
1
Publication Order Number:
MC100LVEP34/D
MC100LVEP34
2.5V / 3.3VECL
÷
2,
÷
4,
÷
8
Clock Generation Chip
The MC100LVEP34 is a low skew
÷
2,
÷
4,
÷
8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The V
BB
pin, an internally
generated voltage supply, is available to this device only. For
single
ended input conditions, the unused differential input is
connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01 F capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip
flop is clocked on the falling edge of
the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon start
up, the internal flip
flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple LVEP34s in a system. Single
ended CLK
input operation is limited to a V
CC
≥
3.0 V in PECL mode, or V
EE
≤
3.0 V in NECL mode.
35 ps Output
to
Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
The 100 Series Contains Temperature Compensation.
PECL Mode Operating Range: V
CC
= 2.375 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
2.375 V to
3.8 V
Open Input Default State
LVDS Input Compatible
Pb
Free Packages are Available*
*For additional information on our Pb
Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
SO
16
D SUFFIX
CASE 751B
1
16
MARKING
DIAGRAMS*
A
L, WL
Y
W, WW = Work Week
= Assembly Location
= Wafer Lot
= Year
1
16
100LVEP34
AWLYWW
TSSOP
16
DT SUFFIX
CASE 948F
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
1
16
100
VP34
ALYW
1
16
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
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