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參數(shù)資料
| 型號(hào)： | MC100LVEP34DTR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip |
| 中文描述： | 100LVE SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 164K |
| 代理商： | MC100LVEP34DTR2 |
MC100LVEP34
http://onsemi.com
7
There are two distinct functional relationships between the Master Reset and Clock:
CASE 1:
If the MR is de
asserted (H
L), while the Clock is still high, the
outputs will follow the second ensuing clock rising edge.
CLK
Q0
Q1
Q2
EN
The EN signal will “freeze” the internal divider flip
flops on the first falling edge of CLK after its assertion. The internal
divider flip
flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge
of CLK, then the internal divider flip
flops will “unfreeze” and continue to their next state count with proper phase rela-
tionships.
Internal Clock
Disabled
Internal Clock
Enabled
MR
CLK
Q0
Q1
Q2
EN
Internal Clock
Disabled
Internal Clock
Enabled
MR
CASE 2: If the MR is de
asserted (H
L), after the Clock has transitioned low, the
outputs will follow the third ensuing clock rising edge.
CASE 1
CASE 2
Figure 2. Timing Diagrams
CLOCK
OUTPUT
MR
T
RR
CLOCK
OUTPUT
MR
T
RR
Figure 3. Reset Recovery Time
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| MC100LVEP34DTR2G | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 2.5V/3.3V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVGP19DT | 制造商:ON Semiconductor 功能描述: |
| MC100M | 制造商:Thomas & Betts 功能描述:M SERIES BLIND INSERT,MALE |
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