參數(shù)資料
型號(hào): MC100LVEL56DWR2G
廠商: ON Semiconductor
文件頁數(shù): 1/7頁
文件大小: 0K
描述: IC MUX 2:1 DUAL DIFF ECL 20-SOIC
標(biāo)準(zhǔn)包裝: 1,000
系列: 100LVEL
類型: 差分?jǐn)?shù)字多路復(fù)用器
電路: 2 x 2:1
獨(dú)立電路: 1
電壓電源: 雙電源
電源電壓: 3 V ~ 3.8 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2008
November, 2008 Rev. 12
1
Publication Order Number:
MC100LVEL56/D
MC100LVEL56
3.3VECL Dual Differential
2:1 Multiplexer
Description
The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low skew
clock or other skew sensitive signals.
The device features both individual and common select inputs to
address both data path and random logic applications.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs are
left open the D input will pull down to VEE, The D input will bias
around VCC/2 forcing the Q output LOW.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
Features
580 ps Typical Propagation Delays
Separate and Common Select
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 3.0 V to 3.8 V
Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL
Q Output will Default LOW with Inputs Open or at VEE
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
*For additional marking information, refer to
Application Note AND8002/D.
MARKING DIAGRAM*
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
SO20 WB
DW SUFFIX
CASE 751D
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
20
1
100LVEL56
AWLYYWWG
http://onsemi.com
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