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參數(shù)資料
| 型號(hào)： | MC100ES8111AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:10 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 100ES |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，PECL |
| 輸出： | HSTL |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 110°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
MC100ES8111 DATASHEET
HSTL CLOCK FANOUT BUFFER
MC100ES8111 Revision 4
6
2009 Integrated Device Technology, Inc.
APPLICATIONS INFORMATION
Test Reference and Output Termination
The MC100ES8111 is designed for high-frequency and low-skew
clock distribution. The high-speed differential outputs are capable of
driving 50
transmission lines and always require a DC termination
to VTT (GND). In order to maintain the tight skew and timing
specifications, it is recommend to terminate the differential outputs
by 50
to GND, with the termination resistor located as close as
possible to the end of the clock transmission line. All DC and AC
specifications apply to this termination method (see the reference
circuit shown in Figure 3 “MC100ES8111 AC Test Reference”). The
MC100ES8111 does not support an output termination to VTT = VX
= 0.75 V (center voltage termination).
Figure 3. MC100ES8111 AC Test Reference
Power Consumption and the Junction Temperature
The power consumption PTOT of the MC100ES8111 depends on
the supply voltages and the DC output termination. The clock
frequency has a negligible effect on PTOT. If all outputs are
terminated by 50
to GND, the device power consumption is
calculated by:
PTOT = VCC ICC + ICCO (VCCO - VX)
For instance, at a supply voltage of VCC = 3.3 V and a termination of
50
to GND, the typical device power consumption is 579 mW at
VCCO = 1.8 V and 474 mW at VCCO = 1.5 V.
To make the optimum use of high clock frequency and low skew
capabilities of the MC100ES8111, the device is specified,
characterized and tested for the junction temperature range of TJ =
0°C to +110°C. Because the exact thermal performance depends on
the PCB type, design, thermal management and natural or forced air
convection, the junction temperature provides an exact way to
correlate the application specific conditions to the published
performance data of this datasheet. The correlation of the junction
temperature range to the application ambient temperature range
and vice versa can be done by calculation:
TJ = TA + Rthja Ptot
Assuming a thermal resistance (junction to ambient) of 54.4°C/W
(2s2p board, 100 ft/min airflow, see Table 8) and a typical power
consumption of 575 mW (all outputs terminated 50 ohms to GND,
VCCO = 1.8 V), the junction temperature of the MC100ES8111 is
approximately TA + 31°C, and the minimum ambient temperature in
this example case calculates to -31°C (the maximum ambient
temperature is 79°C. See Table 8). Exceeding the minimum junction
temperature specification of the MC100ES8111 does not have a
significant impact on the device functionality. However, the
continuous use the MC100ES8111 at high ambient temperatures
requires thermal management to not exceed the specified maximum
junction temperature.
Maintaining Lowest Device Skew
The MC100ES8111 guarantees low output-to-output skew of
max. 80 ps and a part-to-part skew of max. 630 ps
(VCCO = 1.8 V). To ensure low skew clock signals in the application,
both outputs of any differential output pair need to be terminated
identically, even if only one output is used. When fewer than all ten
output pairs are used, identical termination of all output pairs within
the output bank (same package side) is recommended. If an entire
output bank is not used, it is recommended to leave all of these
outputs open and unterminated. This will reduce the device power
consumption while maintaining minimum output skew.
Power Supply Bypassing
The MC100ES8111 is a mixed analog/digital product. The
differential architecture of the MC100ES8111 supports low noise
signal operation at high frequencies. In order to maintain its superior
signal quality, all VCC pins should be bypassed by high-frequency
ceramic capacitors connected to GND. If the spectral frequencies of
the internally generated switching noise on the supply pins cross the
Z = 50
RT = 50
DUT
MC100ES8111
Differential Pulse
Generator
Z = 50
RT = 50
VTT = GND
VCC = 3.3 V ± 5%
VCCO = 1.8 V ± 0.1 V or 1.5 V ± 0. 1 V
Z = 50
Oscilloscope
or Tester
Table 7. Power Consumption
MC100ES8111
PTOT, TYP(1)
1. Typical case: VCC, VCCO at nominal values and using typical
ICC, ICCO data.
PTOT, MAX(2)
2. Worst case: VCC, VCC at max. values and using max. ICC, ICCO
limits.
VCCO = 1.5 V
470 mW
647 mW
VCCO = 1.8 V
575 mW
769 mW
Table 8. Ambient Temperature Ranges (Ptot = 575 mW)
Rthja (2s2p board)
TA, min(1)
1. The MC100ES8111 device function is guaranteed from
TA = -40°C to TJ = 110°C.
TA, max
Natural convection
59.0°C/W
-34°C
76°C
100 ft/min
54.4°C/W
-31°C
79°C
200 ft/min
52.5°C/W
-30°C
80°C
400 ft/min
50.4°C/W
-29°C
81°C
800 ft/min
47.8°C/W
-27.5°C
82.5°C
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