參數(shù)資料
型號: MC100ES6220AER2
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/9頁
文件大小: 0K
描述: IC CLK BUFFER 1:10 1GHZ 52-LQFP
標(biāo)準(zhǔn)包裝: 1,500
系列: 100ES
類型: 扇出緩沖器(分配)
電路數(shù): 2
比率 - 輸入:輸出: 1:10
差分 - 輸入:輸出: 是/是
輸入: ECL,PECL
輸出: LVPECL
頻率 - 最大: 1GHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 52-PTQFP(10x10)
包裝: 帶卷 (TR)
Advanced Clock Drivers Devices
Freescale Semiconductor
5
MC100ES6220
Figure 3. MC100ES6220 AC Test Reference
Figure 4. MC100ES6220 AC Reference Measurement Waveform
Table 6. AC Characteristics (ECL: VEE = –3.3 V ± 5% or VEE = –2.5 V ± 5%, VCC = GND) or
(PECL: VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, VEE = GND, TJ = 0°C to +110°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals)
VPP
Differential Input Voltage(2) (peak-to-peak)
2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and
device-to-device skew.
0.3
1.3
V
VCMR
Differential Input Crosspoint Voltage(3)
PECL
ECL
3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device
propagation delay, device and part-to-part skew.
1.1
VEE + 1.1
VCC – 0.3
–0.3
V
fCLK
Input Frequency
0
1000
MHz
Differential
PECL/ECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9)
tPD
Propagation Delay CLKx to Qx0-9
285
550
ps
Differential
VO(P-P)
Differential Output Voltage (peak-to-peak)
400
600
mV
tsk(O)
Output-to-Output Skew
60
130
ps
Differential
tsk(PP)
Output-to-Output Skew (part-to-part)
200
ps
Differential
tJIT(CC)
Output Cycle-to-Cycle Jitter
RMS (1
σ)1
ps
tSK(P)
DCO
Output Pulse Skew(4)
Output Duty Cycle
fREF < 0.1 GHz
fREF < 1.0 GHz
4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH – tpHL |.
49.65
46.5
50
35
50.35
53.5
ps
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
50
350
ps
20% to 80%
Differential Pulse
Generator
Z = 50
RT = 50
Z = 50
DUT
MC100ES6220
VTT
RT = 50
Z = 50
VTT
tPD (CLKN to QX)
VCMR = VCC – 1.3 V
VPP = 0.8 V
CLKN
QX
MC100ES6220
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
NETCOM
IDT Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6220
5
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