參數(shù)資料
型號: MC100ES6220AER2
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/9頁
文件大小: 0K
描述: IC CLK BUFFER 1:10 1GHZ 52-LQFP
標(biāo)準(zhǔn)包裝: 1,500
系列: 100ES
類型: 扇出緩沖器(分配)
電路數(shù): 2
比率 - 輸入:輸出: 1:10
差分 - 輸入:輸出: 是/是
輸入: ECL,PECL
輸出: LVPECL
頻率 - 最大: 1GHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 52-PTQFP(10x10)
包裝: 帶卷 (TR)
MC100ES6220
Rev 4, 04/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage Dual 1:10 Differential
ECL/PECL Clock Fanout Buffer
The MC100ES6220 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6220
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver are high performance
clock distribution in computing, networking and telecommunication systems.
Features
Two independent 1:10 differential clock fanout buffers
130 ps maximum device skew
SiGe technology
Supports DC to 1 GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL compatible differential clock inputs
Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
Standard 52-lead LQFP package with exposed pad for enhanced thermal
characteristics
Supports industrial temperature range
Pin and function compatible to the MC100EP220
52-lead Pb-free Package Available
Functional Description
The MC100ES6220 is designed for low skew clock distribution systems and
supports clock frequencies up to 1 GHz. The device consists of two independent
clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each
clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA or CLKB input and
bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the VBB
bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6220 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6220 supports positive (PECL) and negative (ECL) supplies. The MC100ES6220 is pin and function compatible to the
MC100EP220.
MC100ES6220
LOW VOLTAGE DUAL
1:10 DIFFERENTIAL ECL/PECL
CLOCK FANOUT BUFFER
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 1336A-01
TB SUFFIX
52-LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A-01
DATA SHEET
MC100ES6220
IDT Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6220
1
Low Voltage Dual 1:10 Differential
ECL/PECL Clock Fanout Buffer
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