參數(shù)資料
型號: MC100ES6014DT
廠商: MOTOROLA INC
元件分類: 時鐘及定時
英文描述: 100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: TSSOP-20
文件頁數(shù): 1/8頁
文件大?。?/td> 110K
代理商: MC100ES6014DT
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MC100ES6014
Rev 2, 5/2004
Motorola, Inc. 2004
2.5V / 3.3V 1:5 Differential
ECL/PECL/HSTL/LVDS Clock Driver
The MC100ES6014 is a low skew 1-to-5 differential driver, designed with
clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or single-
ended (if the VBB output is used). HSTL and LVDS inputs can be used when
the ES6014 is operating under PECL conditions.
The ES6014 specifically guarantees low output-to-output skew. Optimal
design, layout, and processing minimize skew within a device and from device
to device.
To ensure that the tight skew specification is realized, both sides of any
differential output need to be terminated identically into 50
even if only one
output is being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/disabled in
the LOW state. This avoids a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control. The internal flip flop is
clocked on the falling edge of the input clock; therefore, all associated
specification limits are referenced to the negative edge of the clock input.
The MC100ES6014, as with most other ECL devices, can be operated from
a positive VCC supply in PECL mode. This allows the ES6014 to be used for
high performance clock distribution in +3.3 V or +2.5 V systems. Single
ended CLK input pin operation is limited to a VCC ≥ 3.0 V in PECL mode, or
VEE ≤ –3.0 V in ECL mode. Designers can take advantage of the ES6014's
performance to distribute low skew clocks across the backplane or the board.
Features
25 ps Within Device Skew
400 ps Typical Propagation Delay
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
ECL Mode: VCC = 0 V with VEE = –2.375 V to –3.8 V
LVDS and HSTL Input Compatible
Open Input Default State
MC100ES6014
SCALE 2:1
DT SUFFIX
20 LEAD TSSOP PACKAGE
CASE 948E
ORDERING INFORMATION
Device
Package
MC100ES6014DT
TSSOP-20
MC100ES6014DTR2
TSSOP-20
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