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參數(shù)資料
| 型號(hào)： | MC100EP195BMNR4G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 100EP |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.5ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.2ns ~ 12.2ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC100EP195BMNR4GOSCT |
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MC100EP195B
http://onsemi.com
11
Table 10. AC CHARACTERISTICS CC = 0 V; VEE = 3.0 V to 3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 14)
Symbol
Unit
85°C
25°C
40°C
Characteristic
Symbol
Unit
Max
Typ
Min
Max
Typ
Min
Max
Typ
Min
Characteristic
VPP
Input Voltage Swing
(Differential Configuration)
150
800
1200
150
800
1200
150
800
1200
mV
tr
tf
Output Rise/Fall Time @ 50 MHz
2080% (Q)
2080% (CASCADE)
85
110
115
160
140
210
100
120
175
140
230
100
120
130
190
165
250
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
15.Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
16.Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
17.This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
18.This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater
than ±75 mV to that IN/IN transition.
19.This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output re-
sponse greater than ±75 mV to that IN/IN transition.
20.This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
21.Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps.
Figure 4. AC Reference Measurement
IN
Q
tPHL
tPLH
VINPP = VIH(D) VIL(D)
VOUTPP = VOH(Q) VOL(Q)
Cascading Multiple EP195Bs
To increase the programmable range of the EP195B,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP195Bs without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E195B.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range: however, this
increase is at the expense of a longer minimum delay.
Figure 5 illustrates the interconnect scheme for cascading
two EP195Bs. As can be seen, this scheme can easily be
expanded for larger EP195B chains. The D10 input of the
EP195B is the CASCADE control pin. With the
interconnect scheme of Figure 5 when D10 is asserted, it
signals the need for a larger programmable range than is
achievable with a single device and switches output pin
CASCADE HIGH and pin CASCADE LOW. The A11
address can be added to generate a cascade output for the
next EP195B. For a 2device configuration, A11 is not
required.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP195FA | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195FAG | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195FAG | 制造商:ON Semiconductor 功能描述:DELAY LINE IC |
| MC100EP195FAR2 | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195FAR2G | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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