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參數(shù)資料
| 型號： | MC100EP195BMNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-QFN |
| 標準包裝： | 1 |
| 系列： | 100EP |
| 標片/步級數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.5ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.2ns ~ 12.2ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC100EP195BMNR4GOSCT |
MC100EP195B
http://onsemi.com
3
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
D[0:9]
LVCMOS, LVTTL,
ECL Input
Low
SingleEnded Parallel Data Inputs [0:9]. Internal 75 kW to VEE.
(Note 1)
3
D[10]
LVCMOS, LVTTL,
ECL Input
Low
SingleEnded CASCADE/CASCADE Control Input. Internal 75 kW
4
IN
LVPECL, LVDS
Low
Noninverted Differential Input. Internal 75 kW to VEE.
5
IN
LVPECL, LVDS
High
Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to
VCC.
6
VBB
ECL Reference Voltage Output
7
VEF
Reference Voltage for ECL Mode Connection
8
VCF
LVCMOS, ECL, OR LVTTL Input Mode Select
9, 24, 28
VEE
Negative Supply Voltage. All VEE Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
13, 18, 19, 22
VCC
Positive Supply Voltage. All VCC Pins must be externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
10
LEN
ECL Input
Low
Singleended D pins LOAD / HOLD input. Internal 75 kW to VEE.
11
SETMIN
ECL Input
Low
Singleended Minimum Delay Set Logic Input. Internal 75 kW to
12
SETMAX
ECL Input
Low
Singleended Maximum Delay Set Logic Input. Internal 75 kW to
14
CASCADE
ECL Output
Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50 W to VTT = VCC 2 V.
15
CASCADE
ECL Output
Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50 W to VTT = VCC 2 V.
16
EN
ECL Input
Low
Singleended Output Enable Pin. Internal 75 kW to VEE.
17
NC
No Connect. The NC Pin is Electrically Connected to the Die and
”MUST BE” Left Open
21
Q
ECL Output
Noninverted Differential Output. Typically Terminated with 50 W to
VTT = VCC 2 V.
20
Q
ECL Output
Inverted Differential Output. Typically Terminated with 50 W to
VTT = VCC 2 V.
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP195FA | 功能描述:延遲線/計時元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195FAG | 功能描述:延遲線/計時元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195FAG | 制造商:ON Semiconductor 功能描述:DELAY LINE IC |
| MC100EP195FAR2 | 功能描述:延遲線/計時元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195FAR2G | 功能描述:延遲線/計時元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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