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參數(shù)資料
| 型號： | MC100E337FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER |
| 中文描述： | 100E SERIES, 3-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 116K |
| 代理商： | MC100E337FN |
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E337 is a 3-bit registered bus transceiver with scan.
The bus outputs (BUS0–BUS2) are specified for driving a 25
bus; the
receive outputs (Q0 – Q2) are specified for 50
. The bus outputs feature
a normal HIGH level (VOH) and a cutoff LOW level — when LOW, the
outputs go to – 2.0V and the output emitter-follower is “off”, presenting a
high impedance to the bus. The bus outputs also feature edge slow-down
capacitors.
Scannable Version of E336
25
Cutoff Bus Outputs
50
Receiver Outputs
Scannable Registers
Sync. and Async. Bus Enables
Non-inverting Data Path
1500ps Max. Clock to Bus (Data Transmit)
1000ps Max. Clock to Q (Data Receive)
Bus Outputs Feature Internal Edge Slow-Down Capacitors
Additional Package Ground Pins
Extended 100E VEE Range of – 4.2V to – 5.46V
75k
Input Pulldown Resistors
Both drive and receive sides feature the same logic, including a loopback path to hold data. The HOLD/LOAD function is
controlled by Transmit Enable (TEN) and Receive Enable (REN) on the transmit and receive sides respectively, with a HIGH
selecting LOAD. Note that the implementation of the E337 Receive Enable differs from that of the E336.
A synchronous bus enable (SBUSEN) is provided for normal, non-scan operation. The asynchronous bus disable (ABUSDIS)
disables the bus immediately for scan mode.
The SYNCEN input is provided for flexibility when re-enabling the bus after disabling with ABUSDIS, allowing either
synchronous or asynchronous re-enabling. An alternative use is asynchronous-only operation with ABUSDIS, in which case
SYNCEN is tied LOW, or left open. SYNCEN is implemented as an overriding SET control (active-LOW) to the enable flip-flop.
Scan mode is selected by a HIGH at the SCAN input. Scan input data is shifted in through S_IN and output data appears at the
Q2 output.
All registers are clocked on the positive transition of CLK. Additional lead-frame grounding is provided through the Ground pins
(GND) which should be connected to 0V. The GND pins are not electrically connected to the chip.
PIN NAMES
Pin
Function
A0– A2
B0– B2
S-IN
TEN, REN
SCAN
ABUSDIS
SBUSEN
SYNCEN
CLK
BUS0 – BUS2
Q0– Q2
Data Inputs A
Data Inputs B
Serial (Scan) Data Input
HOLD/LOAD Controls
Scan Control
Asynchronous Bus Disable
Synchronous Bus Enable
Synchronous Enable Control
Clock
25
Cutoff Bus Outputs
Receive Data Outputs (Q2 serves as SCAN_OUT in scan mode)
3-BIT SCANNABLE
REGISTERED
BUS TRANSCEIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
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| MC10E337 | Relays; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Features:SNAP OEM I/O Programmable Brain |
| MC10E337FN | 3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER |
| MC100E431FN | 3-BIT DIFFERENTIAL FLIP-FLOP |
| MC10E431 | 0.345A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC 0 to 85 |
| MC10E431FN | 0.345A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC 0 to 85 |
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