參數(shù)資料
型號: MC10E431
廠商: ON SEMICONDUCTOR
英文描述: 0.345A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC 0 to 85
中文描述: 3位微分觸發(fā)器
文件頁數(shù): 1/4頁
文件大?。?/td> 109K
代理商: MC10E431
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 3
Motorola, Inc. 1996
5/95
The MC10E/100E431 is a 3-bit flip-flop with differential clock, data
input and data output.
The asynchronous Set and Reset controls are edge-triggered rather
than level controlled. This allows the user to rapidly set or reset the
flip-flop and then continue clocking at the next clock edge, without the
necessity of de-asserting the set/reset signal (as would be the case with a
level controlled set/reset).
The E431 is also designed with larger internal swings, an approach
intended to minimize the time spent crossing the threshold region and
thus reduce the metastability susceptibility window.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of the
inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the input
clamps only operate when both inputs fall to 2.5V below VCC.
Edge-Triggered Asynchronous Set and Reset
Differential D, CLK and Q; VBB Reference Available
1100MHz Min. Toggle Frequency
Extended 100E VEE Range of – 4.2V to – 5.46V
Pinout: 28-Lead PLCC
(Top View)
PIN NAMES
Pin
Function
D
[
0:2
]
, D
[
0:2
]
CLK
[
0:2
]
, CLK
[
0:2
]
S
[
0:2
]
R
[
0:2
]
VBB
Q
[
0:2
]
, Q
[
0:2
]
Differential Data Inputs
Differential Clock
Edge Triggered Set Inputs
Edge Triggered Reset Input
VBB Reference Output
Differential Data Outputs
3-BIT DIFFERENTIAL
FLIP-FLOP
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
CLK0 CLK0
D0
D0
R0
D2
D2
CLK2
CLK2
VBB
VCCO
LOGIC DIAGRAM
CLK1
CLK1
R1
VEE
S1
D1
D1
26
27
28
2
3
4
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
5
6
7
8
9
10
R2
S2
Q2
Q2
VCC
Q1
Q1
Q0
Q0
S0
S0
D0
D0
CLK0
CLK0
R0
S1
D1
D1
CLK1
CLK1
R1
S2
D2
D2
CLK2
CLK2
R2
VBB
Q0
Q0
Q1
Q1
Q2
Q2
S
Q
R
Q
D
S
Q
R
Q
D
S
Q
R
Q
D
1
* All VCC and VCCO pins are tied together on the die.
相關(guān)PDF資料
PDF描述
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