參數(shù)資料
型號(hào): MC-4R512FKE6D-653
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: Direct Rambus DRAM RIMM Module 512M-BYTE (256M-WORD x 16-BIT)
中文描述: 256M X 16 DIRECT RAMBUS DRAM MODULE, 53 ns, DMA184
封裝: SOCKET TYPE, RIMM-184
文件頁(yè)數(shù): 9/14頁(yè)
文件大小: 132K
代理商: MC-4R512FKE6D-653
Data Sheet
E0077N20 (Ver 2.0)
9
MC-4R512FKE6D
AC Electrical Specifications
Symbol
Parameter and Conditions
MIN.
TYP.
MAX.
Unit
Z
Module Impedance of RSL signals
25.2
28.0
30.8
Module Impedance of SCK and CMD signals
23.8
28.0
32.2
T
PD
Average clock delay from finger to finger of all RSL clock nets
2.11
ns
(CTM, CTMN,CFM, and CFMN)
T
PD
Propagation delay variation of RSL signals with respect to TPD
Note1,2
24
+24
ps
T
PD-CMOS
Propagation delay variation of SCK signal with respect to an average clock
delay
Note1
250
+250
ps
T
PD- SCK,CMD
Propagation delay variation of CMD signal with respect to SCK signal
200
+2
0
0
ps
V
α
/V
IN
Attenuation Limit
-845
25.0
%
-745
25.0
-653
18.5
V
XF
/V
IN
Forward crosstalk coefficient
-845
8.0
%
(300ps input rise time 20% - 80%)
-745
8.0
-653
8.0
V
XB
/V
IN
Backward
crosstalk coefficient
-845
2.5
%
(300ps input rise time 20% - 80%)
-745
2.5
-653
2.5
R
DC
DC Resistance Limit
-845
1.2
-745
1.2
-653
1.2
Notes 1.
T
PD
or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2.
If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted
T
PD
Specification” table.
Adjusted
T
PD
Specification
Symbol
Parameter and conditions
Adjusted MIN./MAX.
Absolute
Unit
MIN.
MAX.
T
PD
Propagation delay variation of RSL signals with respect to T
PD
+/
[24+(18*N*
Z0)]
Note
50
50
ps
Note
N = Number of RDRAM devices installed on the RIMM module.
Z0 = delta Z0
%
= (MAX. Z0
MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
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