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參數(shù)資料
| 型號： | MC-4532DC726 |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-Word By72-BIT Dynamic RAM Module(32M×72位動態(tài)RAM模塊) |
| 中文描述： | 32M的詞By72位動態(tài)內存模塊（32M的× 72位動態(tài)內存模塊） |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 174K |
| 代理商： | MC-4532DC726 |
9
MC-4532DC726
Synchronous Characteristics (Registered Mode)
Parameter
Symbol
-A80
-A10
Unit
Note
MIN.
MAX.
MIN.
MAX.
Clock cycle time
/CAS latency = 3
t
CK3
8
(125 MHz)
10
(100 MHz)
ns
/CAS latency = 2
t
CK2
10
(100 MHz)
13
(77 MHz)
ns
Access time from CLK /CAS latency = 3
t
AC3
6
6
ns
1
/CAS latency = 2
t
AC2
6
7
ns
1
Input CLK duty cycle
40
60
40
60
%
Data-out hold time
/CAS latency = 3
t
OH3
3
3
ns
1
/CAS latency = 2
t
OH2
3
3
ns
1
Data-out low-impedance time
t
LZ
0
0
ns
Data-out high-
/CAS latency = 3
t
HZ3
3
6
3
6
ns
impedance time
/CAS latency = 2
t
HZ2
3
6
3
7
ns
Data-in setup time
t
DS
2
2
ns
Data-in hold time
t
DH
1
1
ns
Address setup time
t
AS
1.5
1.5
ns
Address hold time
t
AH
0.9
0.9
ns
CKE setup time
t
CKS
1.5
1.5
ns
CKE hold time
t
CKH
0.9
0.9
ns
CKE setup time (Power down exit)
t
CKSP
1.5
1.5
ns
Command (/CS0 - /CS3, /RAS, /CAS,
/WE, DQMB0 - DQMB7) setup time
t
CMS
1.5
1.5
ns
Command (/CS0 - /CS3, /RAS, /CAS,
/WE, DQMB0 - DQMB7) hold time
t
CMH
0.9
0.9
ns
Note 1.
Output load
Output
Z = 50
1.4 V
50 pF
50
Remark
These specifications are applied to the monolithic device.
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