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參數(shù)資料
| 型號： | MC-4532DA726 |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-Word By 72-BIT Dynamic RAM Module(動態(tài)RAM模塊) |
| 中文描述： | 32M的詞由72位動態(tài)內(nèi)存模塊（動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 150K |
| 代理商： | MC-4532DA726 |
6
MC-4532DA726
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
-A80
2,280
mA
1
/CAS latency = 2
-A10
2,010
-A80
2,370
Operating current
I
CC1
Burst length
=
1, t
RC
≥
t
RC(MIN.)
,
I
O
= 0
mA
/CAS latency = 3
-A10
2,100
Precharge standby current in I
CC2
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
268
mA
power down mode
I
CC2
PS CKE
≤
V
IL(MAX.)
, t
CK
=
∞
19
Precharge standby current in
non power down mode
I
CC2
N CKE
≥
V
IH (MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH (MIN.)
,
Input signals are changed one time during 30
ns.
I
CC2
NS CKE
≥
V
IH (MIN.)
, t
CK
=
∞
, Input signals are stable.
610
mA
108
Active standby current in
I
CC3
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
340
mA
power down mode
I
CC3
PS CKE
≤
V
IL(MAX.)
, t
CK
=
∞
72
Active standby current in
I
CC3
N CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
700
mA
non power down mode
Input signals are changed one time during 30
ns.
I
CC3
NS CKE
≥
V
IH (MIN.)
, t
CK
=
∞
, Input signals are stable.
216
Operating current
I
CC4
t
CK
≥
t
CK(MIN.)
, I
O
= 0
mA
/CAS latency = 2
-A80
2,100
mA
2
(Burst mode)
-A10
1,740
/CAS latency = 3
-A80
2,370
-A10
2,100
Refresh current
I
CC5
t
RC
≥
t
RC(MIN.)
/CAS latency = 2
-A80
4,980
mA
3
-A10
4,620
/CAS latency = 3
-A80
5,160
-A10
4,800
Self refresh current
I
CC6
CKE
≤
0.2
V
286
mA
Input leakage current
I
I(L)
V
I
=
0 to 3.6
V,
All other pins not under test =
0 V
–
10
+
10
μ
A
Output leakage current
I
O(L)
D
OUT
is disabled, V
O
=
0 to 3.6
V
–
1.5
+
1.5
μ
A
High level output voltage
V
OH
I
O
=
–
4.0
mA
2.4
V
Low level output voltage
V
OL
I
O
=
+
4.0
mA
0.4
V
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
2
. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MC-4532DA726EFB-A10 | 制造商:NEC 制造商全稱:NEC 功能描述:32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
| MC-4532DA726EFB-A80 | 制造商:NEC 制造商全稱:NEC 功能描述:32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
| MC-4532DA726PFB-A10 | 制造商:NEC 制造商全稱:NEC 功能描述:32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
| MC-4532DA726PFB-A80 | 制造商:NEC 制造商全稱:NEC 功能描述:32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
| MC-4532DA726XFB-A10 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
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