參數(shù)資料
型號(hào)： MBM29LV001TC-55PD
廠商： FUJITSU LTD
元件分類： DRAM
英文描述： GLAND PACK 3 TO 5MM
中文描述： 128K X 8 FLASH 3V PROM, 55 ns, PQCC32
封裝： PLASTIC, LCC-32
文件頁(yè)數(shù)： 22/49頁(yè)
文件大?。?/td> 421K
代理商： MBM29LV001TC-55PD
MBM29LV001TC
-55/-70
/MBM29LV001BC
-55/-70
22
Notes:
1. Performing successive read operations from any address will cause DQ
6
to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ
2
bit. However, successive reads from the erase-suspended sector will cause DQ
2
to
toggle.
RESET
Hardware Reset
The MBM29LV001TC/BC devices may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse
requirement and has to be kept low (V
IL
) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20
μ
s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional t
RH
before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. See
Figure 12 for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
Data Protection
The MBM29LV001TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 2.3 V (typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
Toggle
1
Erase
0
Toggle
Toggle
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
Toggle
Erase-Suspend Program
DQ
7
Toggle (Note 1)
1 (Note 2)
相關(guān)PDF資料
PDF描述
MBM29LV001TC-55PFTN 1M (128K x 8) BIT
MBM29LV001TC-55PFTR 1M (128K x 8) BIT
MBM29LV001TC-70 1M (128K x 8) BIT
MBM29LV001TC-70PD 1M (128K x 8) BIT
MBM29LV001TC-70PFTN 1M (128K x 8) BIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29LV001TC-55PFTN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
MBM29LV001TC-55PFTR 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
MBM29LV001TC-70 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
MBM29LV001TC-70PD 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
MBM29LV001TC-70PFTN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*