參數(shù)資料
型號(hào)： MBM29LV001TC-55PD
廠商： FUJITSU LTD
元件分類： DRAM
英文描述： GLAND PACK 3 TO 5MM
中文描述： 128K X 8 FLASH 3V PROM, 55 ns, PQCC32
封裝： PLASTIC, LCC-32
文件頁數(shù)： 15/49頁
文件大?。?/td> 421K
代理商： MBM29LV001TC-55PD
15
MBM29LV001TC
-55/-70
/MBM29LV001BC
-55/-70
Byte Programming
The devices are programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are
two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses
are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge
of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required
to provide further controls or timings. The device will automatically provide adequate internally generated
program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 17 illustrates the Embedded Program
TM
Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the last write pulse in the command sequence and terminates
when the data on DQ
7
is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
Chip Erase Time; Sector Erase Time
×
All sectors + Chip Program Time (Preprogramming)
Figure 18 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
相關(guān)PDF資料
PDF描述
MBM29LV001TC-55PFTN 1M (128K x 8) BIT
MBM29LV001TC-55PFTR 1M (128K x 8) BIT
MBM29LV001TC-70 1M (128K x 8) BIT
MBM29LV001TC-70PD 1M (128K x 8) BIT
MBM29LV001TC-70PFTN 1M (128K x 8) BIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29LV001TC-55PFTN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
MBM29LV001TC-55PFTR 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
MBM29LV001TC-70 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
MBM29LV001TC-70PD 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
MBM29LV001TC-70PFTN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:1M (128K x 8) BIT
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