參數(shù)資料
型號(hào): MBM29F800TA-70PFTN
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 8M (1M X 8/512K X 16) BIT
中文描述: 512K X 16 FLASH 5V PROM, 70 ns, PDSO48
封裝: PLASTIC, TSOP1-48
文件頁(yè)數(shù): 26/48頁(yè)
文件大?。?/td> 537K
代理商: MBM29F800TA-70PFTN
26
MBM29F800TA
-55/-70/-90
/MBM29F800BA
-55/-70/-90
I
AC CHARACTERISTICS
Read Only Operations Characteristics
Note:
1. Test Conditions:
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
Parameter
Symbols
Description
Test Setup
MBM29F800TA/BA
Unit
JEDEC
Standard
-55
(Note1)
-70
(Note2)
-90
(Note2)
t
AVAV
t
RC
Read Cycle Time
Min.
55
70
90
ns
t
AVQV
t
ACC
Address to Output Delay
CE = V
IL
OE = V
IL
Max.
55
70
90
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE = V
IL
Max.
55
70
90
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max.
30
30
40
ns
t
EHQZ
t
DF
Chip Enable to Output High-Z
Max.
15
20
20
ns
t
GHQZ
t
DF
Output Enable to Output High-Z
Max.
15
20
20
ns
t
AXQX
t
OH
Output Hold Time From
Addresses, CE or OE, Whichever
Occurs First
Min.
0
0
0
ns
t
READY
RESET Pin Low to Read Mode
Max.
20
20
20
μ
s
t
ELFL
t
ELFH
CE or BYTE Switching Low or
High
Max.
5
5
5
ns
Figure 4 Test Conditions
C
L
5.0 V
Diodes = IN3064
or Equivalent
2.7 k
Device
Under
Test
IN3064
or Equivalent
6.2 k
Notes:
1. C
L
= 30 pF including jig capacitance (MBM29F800TA/BA-55)
2. C
L
= 100 pF including jig capacitance (MBM29F800TA/BA-70/-90)
Note:
2. Test Conditions:
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level
Input: 0.8 V and 2.0 V
Output: 0.8 V and 2.0 V
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