參數(shù)資料
型號: MBM29F080-90
廠商: Fujitsu Limited
英文描述: 8M (1M ×8) BIT Flash Memory(1M ×8 位5V 電源電壓閃速存儲器)
中文描述: 8米(1米× 8)位快閃記憶體(1米× 8位5V的電源電壓閃速存儲器)
文件頁數(shù): 18/50頁
文件大?。?/td> 667K
代理商: MBM29F080-90
18
MBM29F080
-90/-12
these conditions DQ
5
will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the device under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Table 2.
The DQ
5
failure condition may also appear if a user tries to program a 1 to a location that is previously programmed
to 0. In this case the device locks out and never completes the Embedded Program Algorithm. Hence, the system
never reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the device has exceeded timing limits,
the DQ
5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly
used. If this occurs, reset the device.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will
be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low (“0”),
the device will accept additional sector erase commands. To insure the command has been accepted, the system
software should check the status of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
were high on the second status check, the command may not have been accepted.
Refer to Table 7: Hardware Sequence Flags
DQ
2
Toggle Bit 2
This toggle bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
Notes: 1.These status flags apply when outputs are read from a sector that has been erase-suspended.
2.These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
toggles
1
Erase
0
toggles
toggles
Erase Suspend Read (1)
(Erase-Suspended Sector)
1
1
toggles
Erase Suspend Program
DQ
7
(2)
toggles
1 (2)
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