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參數(shù)資料
| 型號(hào)： | MB9AF312LPMC1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 7/114頁(yè) |
| 文件大?。?/td> | 1357K |
| 代理商： | MB9AF312LPMC1 |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
104
16.6
Input Capture Unit
The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp
indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or
alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and
other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.
The input capture unit is illustrated by the block diagram shown in Figure 16-3. The elements of the block diagram that are
not directly a part of the input capture unit are gray shaded. The small “n” in register and bit names indicates the
Timer/Counter number.
Figure 16-3. Input Capture Unit Block Diagram
When a change of the logic level (an event) occurs on the input capture pin (ICP1), alternatively on the analog comparator
output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is
triggered, the 16-bit value of the counter (TCNT1) is written to the input capture register (ICR1). The input capture flag (ICF1)
is set at the same system clock as the TCNT1 value is copied into ICR1 register. If enabled (ICIE1 = 1), the input capture flag
generates an input capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the
ICF1 flag can be cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the input capture register (ICR1) is done by first reading the low byte (ICR1L) and then the high
byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the
CPU reads the ICR1H I/O location it will access the TEMP register.
The ICR1 register can only be written when using a waveform generation mode that utilizes the ICR1 register for defining the
counter’s TOP value. In these cases the waveform generation mode (WGM13:0) bits must be set before the TOP value can
be written to the ICR1 register. When writing the ICR1 register the high byte must be written to the ICR1H I/O location before
the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to Section 16.3 “Accessing 16-bit Registers” on page 100.
ICFn (Int. Req.)
ICRnL (8-bit)
ICRnH (8-bit)
ICRn (16-bit Register)
TEMP (8-bit)
TCNTnL (8-bit)
TCNTnH (8-bit)
TCNTn (16-bit Counter)
DATA BUS (8-bit)
Noise
Canceler
Analog
Comparator
Edge
Detector
ICNC
ACIC*
ACO*
WRITE
+
-
ICES
ICPn
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB9AF312MPMC | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80 |
| MB9AF312LPMC | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64 |
| MB9AF311NPMC | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100 |
| MB9AF316NPMC | RISC MICROCONTROLLER, PQFP100 |
| MB9AF314NPMC | RISC MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB9AF314LAPMC1-G-JNE2 | 制造商:FUJITSU 功能描述: |
| MB9AF314LAPMC-G-JNE2 | 制造商:Fujitsu 功能描述:Bulk |
| MB9AF314LAQN-G-AVE2 | 功能描述:ARM? Cortex?-M3 FM3 MB9A310A Microcontroller IC 32-Bit 40MHz 256KB (256K x 8) FLASH 64-QFN Exposed Pad (9x9) 制造商:cypress semiconductor corp 系列:FM3 MB9A310A 包裝:托盤 零件狀態(tài):有效 核心處理器:ARM? Cortex?-M3 核心尺寸:32-位 速度:40MHz 連接性:CSIO，I2C，LIN，UART/USART，USB 外設(shè):DMA，LVD，POR，PWM，WDT I/O 數(shù):51 程序存儲(chǔ)容量:256KB（256K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 容量:- RAM 容量:32K x 8 電壓 - 電源（Vcc/Vdd）:2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 9x12b 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 105°C（TA） 封裝/外殼:64-VFQFN 裸露焊盤 供應(yīng)商器件封裝:64-QFN 裸露焊盤（9x9） 標(biāo)準(zhǔn)包裝:260 |
| MB9AF314LPMC1-ESE1 | 制造商:FUJITSU 功能描述: |
| MB9AF314LPMC1-GE1 | 制造商:FUJITSU 功能描述: |
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