I2C Timing *1 : For use at over 100 kHz, s" />
參數(shù)資料
型號(hào): MB96F387RSBPMC-GSE2
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 5/132頁
文件大?。?/td> 0K
描述: IC MCU 416KB FLASH/ROM 120LQFP
標(biāo)準(zhǔn)包裝: 1
系列: F²MC MB96380
核心處理器: F²MC-16FX
芯體尺寸: 16-位
速度: 56MHz
連通性: CAN,EBI/EMI,I²C,LIN,SCI,UART/USART
外圍設(shè)備: DMA,LCD,LVD,LVR,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲(chǔ)器容量: 416KB(416K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 120-LQFP
包裝: 托盤
其它名稱: 865-1089
MB96380 Series
102
FME-MB96380 rev 10
I2C Timing
*1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
*2 : Cb = capacitance of one bus line in pF.
*3 : tCLKP1 is the cycle time of the periperal clock CLKP1.
VOH = 0.7 * VCC
VOL = 0.3 * VCC
CMOS Hysteresis 0.7/0.3 input selected
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Standard-mode
Fast-mode*1
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA
↓→SCL↓
tHDSTA
4.0
0.6
s
“L” width of the SCL clock
tLOW
4.7
1.3
s
“H” width of the SCL clock
tHIGH
4.0
0.6
s
Set-up time for a repeated START condition
SCL
↑→SDA↓
tSUSTA
4.7
0.6
s
Data hold time
SCL
↓→SDA↓↑
tHDDAT
0
3.45
0
0.9
s
Data set-up time
SDA
↓↑→SCL↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL
↑→SDA↑
tSUSTO
4.0
0.6
s
Bus free time between a STOP and START
condition
tBUS
4.7
1.3
s
Output fall time from 0.7*Vcc to 0.3*Vcc with
a bus capacitance from 10 pF to 400 pF
tof
20 + 0.1*Cb *2
250
20 + 0.1*Cb *2
250
ns
Capacitive load for each bus line
Cb
400
400
pF
Pulse width of spikes which will be sup-
pressed by input noise filter
tSP
n/a
0
1*tCLKP1*3
ns
SDA
SCL
tLOW
tSUDAT
tHDSTA
tBUS
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
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