參數(shù)資料
型號： MB95FV100D-103
廠商： Fujitsu Limited
英文描述： 8-bit Proprietary Microcontrollers(8位微控制器)
中文描述： 8位微控制器專利（8位微控制器）
文件頁數(shù)： 58/72頁
文件大?。?/td> 739K
代理商： MB95FV100D-103
MB95100AM Series
58
(Continued)
(Vcc
=
5.0 V
±
10
%
, AVss
=
Vss
=
0.0 V, T
A
=
40
°
C to
+
85
°
C)
Value*
2
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 :
Refer to “ (2) Source Clock/Machine Clock” for t
MCLK
.
m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR0) .
n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR0) .
Actual timing of I
2
C is determined by m and n values set by the machine clock (t
MCLK
) and CS4 to CS0 of
ICCR0 register.
Standard-mode :
m and n can be set at the range : 0.9 MHz < t
MCLK
(machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n)
=
(1, 8)
(m, n)
=
(1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < t
MCLK
≤
2 MHz
(m, n)
=
(1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < t
MCLK
≤
4 MHz
(m, n)
=
(1, 98)
Fast-mode :
m and n can be set at the range : 3.3 MHz < t
MCLK
(machine clock) < 10 MHz.
Setting of m and n limits the machine clock that can be used below.
(m, n)
=
(1, 8)
: 3.3 MHz < t
MCLK
≤
4 MHz
(m, n)
=
(1, 22) , (5, 4) : 3.3 MHz < t
MCLK
≤
8 MHz
(m, n)
=
(6, 4)
: 3.3 MHz < t
MCLK
≤
10 MHz
: 0.9 MHz < t
MCLK
≤
1 MHz
: 0.9 MHz < t
MCLK
≤
10 MHz
Parameter
Sym-
bol
Pin
name
Condition
Unit
Remarks
Min
Max
Data hold time
t
HD;DAT
SCL0
SDA0
R
=
1.7 k
,
C
=
50 pF*
1
0
ns
At reception
Data setup time
t
SU;DAT
SCL0
SDA0
t
MCLK
20
ns
At reception
SDA
↓→
SCL
↑
(at wake-up function)
t
WAKEUP
SCL0
SDA0
Oscillation stabilization
wait time
+
2 t
MCLK
20
ns
相關PDF資料
PDF描述
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相關代理商/技術參數(shù)
參數(shù)描述
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