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| 型號(hào)： | MB95F418KPMC-G-SNE2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁(yè)數(shù)： | 59/76頁(yè) |
| 文件大?。?/td> | 3707K |
| 代理商： | MB95F418KPMC-G-SNE2 |
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MB95410H/470H Series
62
DS702-00004-0v01-E
(8) I2C Timing
(VCC = 5.0 V
± 10%, AVSS = VSS = 0.0 V, TA = 40° C to + 85° C)
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding
the SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition
of tSU;DAT
≥ 250 ns is fulfilled.
(Continued)
Parameter
Symbol Pin name Conditions
Value
Unit
Standard-
mode
Fast-mode
MinMax
SCL clock frequency
fSCL
SCL
R = 1.7 k
Ω,
C = 50 pF*1
01000
400
kHz
(Repeat) Start condition hold time
SDA
↓→SCL ↓
tHD;STA
SCL, SDA
4.0
—
0.6
—
s
SCL clock “L” width
tLOW
SCL
4.7
—
1.3
—
s
SCL clock “H” width
tHIGH
SCL
4.0
—
0.6
—
s
(Repeat) Start condition setup time
SCL
↑ →SDA ↓
tSU;STA
SCL, SDA
4.7
—
0.6
—
s
Data hold time
SCL
↓→SDA ↓↑
tHD;DAT
SCL, SDA
0
3.45*2
00.9*3
s
Data setup time
SDA
↓↑ →SCL ↑
tSU;DAT
SCL, SDA
0.25
—
0.1
—
s
Stop condition setup time
SCL
↑ →SDA ↑
tSU;STO
SCL, SDA
4.0
—
0.6
—
s
Bus free time between stop condition
and start condition
tBUF
SCL, SDA
4.7
—
1.3
—
s
SDA
SCL
tWAKEUP
tHD;STA
tSU;DAT
fSCL
tHD;STA
tSU;STA
tLOW
tHD;DAT
tHIGH
tSU;STO
tBUF
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