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參數(shù)資料
| 型號： | MB95F108AKSPFM |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 46/63頁 |
| 文件大?。?/td> | 749K |
| 代理商： | MB95F108AKSPFM |
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MB95100AH Series
50
(Vcc
= 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
(Continued)
Parameter
Sym-
bol
Pin
name
I/O Timing
Unit
Remarks
Min
Max
SCL clock “L” width
tLOW
SCL0
(2
+ nm*2 / 2)
MCLK*1
20
ns
Master mode
SCL clock “H” width
tHIGH
SCL0
(nm*2
/ 2)
MCLK*1
20
(nm*2
/ 2 )
MCLK*1
+ 20
ns
Master mode
Start condition hold time
tHD;STA
SCL0
SDA0
(
1 + nm*2 / 2)
MCLK*1
20
(
1 + nm*2)
MCLK*1
+ 20
ns
Master mode
Maximum value is applied
when m, n
= 1, 8.
Otherwise, the minimum
value is applied.
Stop condition setup time tSU;STO
SCL0
SDA0
(1
+ nm*2 / 2)
MCLK*1
20
(1
+ nm*2 / 2)
MCLK*1
+ 20
ns
Master mode
Start condition setup time tSU;STA
SCL0
SDA0
(1
+ nm*2 / 2)
MCLK*1
20
(1
+ nm*2 / 2)
MCLK*1
+ 20
ns
Master mode
Bus free time between
stop condition and start
condition
tBUF
SCL0
SDA0
(2 nm*2
+ 4)
MCLK*1
20
ns
Data hold time
tHD;DAT
SCL0
SDA0
3 MCLK*1
20
ns
Master mode
Data setup time
tSU;DAT
SCL0
SDA0
(
2 + nm*2 / 2)
MCLK*1
20
(
1 + nm*2 / 2)
MCLK*1
+ 20
ns
Master mode
When assuming that “L” of
SCL is not extended,
the minimum value is applied
to first bit of continuous data.
Otherwise, the maximum
value is applied.
Setup time between
clearing interrupt and
SCL rising
tSU;INT
SCL0
(nm*2
/ 2)
MCLK*1
20
(1 + nm*2
/ 2)
MCLK*1
+ 20
ns
Minimum value is applied to in-
terrupt at 9th SCL
↓.
Maximum value is applied to
interrupt at 8th SCL
↓.
SCL clock “L” width
tLOW
SCL0
4 MCLK*1
20
ns
At reception
SCL clock “H” width
tHIGH
SCL0
4 MCLK*1
20
ns
At reception
Start condition detection
tHD;STA
SCL0
SDA0
2 MCLK*1
20
ns
Undetected when 1 MCLK is
used at reception
Stop condition detection
tSU;STO
SCL0
SDA0
2 MCLK*1
20
ns
Undetected when 1 MCLK is
used at reception
Restart condition
detection condition
tSU;STA
SCL0
SDA0
2 MCLK*1
20
ns
Undetected when 1 MCLK is
used at reception
Bus free time
tBUF
SCL0
SDA0
2 MCLK*1
20
ns
At reception
Data hold time
tHD;DAT
SCL0
SDA0
2 MCLK*1
20
ns
At slave transmission mode
Data setup time
tSU;DAT
SCL0
SDA0
tLOW
3 MCLK*1
20
ns
At slave transmission mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB95F108AMS | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95F108AMSPFM | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95F108AMSPFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95F108AMW | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95F108AMWPFM | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
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