
MB91270/280 Series
2
Instruction optimized for embedded applications:
Memory-to-memory transfer, bit manipulation, barrel shift instruction etc.
Instructions adapted for high - level languages:
Function entry/exit instructions, multiple - register load/store instructions
Register interlock functions:
Facilitating coding in assemblers
Built-in multiplier supported at the instruction level.
Signed 32-bit multiplication: 5 cycles.
Signed 16-bit multiplication: 3 cycles.
Interrupt (PC, PS save): 6 cycles, 16 priority levels
Harvard architecture allowing program access and data access to be executed simultaneously
Instruction compatible with FR family
External bus interface
Maximum operating frequency: 16 MHz
Can output full 24-bit address range (16 Mbyte space)
8,16-bit data output
Unused data/address pin can be used as general-purpose I/O ports.
Capable of chip select output for completely independent four areas settable in 64 Kbytes minimum.
Supports the following memory interfaces
SRAM, ROM/Flash
Basic bus cycle: 2 cycles
Programmable automatic wait cycle generation function capable of inserting wait cycles for each area
RDY input for external wait cycles
Built-in memory
The peripheral circuits are described below.
See “■PRODUCT LINEUP” for the number of available channels on each model.
DMAC (DMA Controller)
Capable of simultaneous operation of up to five channels
Two forwarding factors (internal peripheral/software)
Bit search module (for REALOS)
Search for the position of the bit “1”/“0”-changed first in one word from the MSB
LIN UARTs (LIN-UART) : Up to 7 channels
Asynchronous (start-stop synchronous) communications, clock synchronous communications
Synch-Break detection
Built-in baud rate generator on each channel
Supports SPI (mode 2: Clock synchronous communication mode)
CAN CONTROLLERS : 3 channels (Max)
High-speed transfer : 1 Mbps
32 message buffer (128 message buffer on the MB91V280)
(Continued)
MB91V280
MB91F272 (S)
ROM/Flash
External SRAM
Flash 256 Kbytes
F-bus RAM
48 Kbytes
10 Kbytes