參數(shù)資料
型號： MB91FV310A
廠商： Fujitsu Limited
英文描述： Proprietary 32-bit Microcontroller CMOS
中文描述： 專有的32位微控制器的CMOS
文件頁數(shù)： 53/59頁
文件大小： 599K
代理商： MB91FV310A
MB91310 Series
53
(8) Digital RGB
Vertical sync, horizontal sync, and display output control signal input timings
(Ta
=
10
°
C to
+
70
°
C, V
DDE
=
3.3 V
±
0.3 V, V
DDI
=
2.5 V
±
0.2 V, Vss
=
0 V)
*1 : During the horizontal sync signal pulse period, the device stops its internal OSDC operation, disabling writing
to the internal VRAM. Therefore, set the horizontal sync signal pulse width and VRAM write cycle to ensure
that: horizontal sync signal pulse width < VRAM write cycle.
Precisely, adjust the command issuance interval not to issue command 2 or command 4 (VRAM write command)
more than once in the horizontal sync signal pulse with period.
If the above condition is not satisfied, the device may fail writing to VRAM.
*2 : 1H is assumed to be one horizontal sync signal period.
Parameter
Symbol
Pin
Value
Unit
Remarks
Min
Max
6
1H*
2
5
Horizontal sync signal cycle time
t
HCYC
HSYNC
100
+
t
WH
20
4
Dot clock
Horizontal sync signal pulse width
t
WH
HSYNC
Dot clock
μ
s
ns
*1
Horizontal sync signal setup time
t
DHST
HSYNC
Horizontal sync signal hold time
t
DHHD
0
ns
Vertical sync signal setup time
t
HVST
VSYNC
5
Dot clock
Vertical sync signal hold time
t
HVHD
3
H*
2
Input sync signal rise/fall time
t
DR
t
DF
HSYNC
VSYNC
5
ns
DOCKI
HSYNC
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
t
DHST
t
DHHD
t
DR
, t
DF
Horizontal sync, and display output control signal input timings
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