參數(shù)資料
型號： MB91FV310A
廠商： Fujitsu Limited
英文描述： Proprietary 32-bit Microcontroller CMOS
中文描述： 專有的32位微控制器的CMOS
文件頁數(shù)： 19/59頁
文件大?。?/td> 599K
代理商： MB91FV310A
MB91310 Series
19
The D0 and D1 flags are updated in advance.
An EIT handling routine (user interrupt, NMI, or emulator) is executed.
Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated
to the same values as in (1).
2. The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed.
The PS register is updated in advance.
An EIT handling routine (user interrupt or NMI) is executed.
Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same
value as in (1).
(7) Watchdog Timer
The watchdog timer built in this model monitors a program to check that it defers a reset within a certain period
of time. The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function
from being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps
on watching programs until it resets the CPU.
As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
program execution.Refer to the watchdog timer function description for the exceptional condition.
If the system runs out of control and develops the above condition, a watchdog reset may not be generated.
In that case, please reset (INIT) by external INIT terminal.
(8) Notes on using the A/D converter
The MB91310 series contains an A/D converter. Supply power to the AV
CC
at 3.3 V.
Unique to the evaluation chip MB91FV310A
(1) Simultaneous occurrences of a software break and a user interrupt/NMI
If a software break and a user interrupt/NMI occurs simultaneously, the emulator debugger may react as follows.
The debugger stops pointing to a location other than the programmed break points.
The halted program is not re - executed correctly.
If this symptom occurs, use a hardware break in place of a hardware break. If you use the monitor debugger,
do not set a break point within the relevant array of instructions.
(2) Single-stepping of the RETI instruction
If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly
after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being exe-
cuted. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant
interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.
(3) About an Operand Break
Do not apply a data event break to access to the area containing the address of a stack pointer.
(4) Sample Batch File for Configuration
To debug a program downloaded to internal RAM, be sure to execute the following batch file after executing
RESET.
# Set MODR (0x7fd)
=
Enable In memory
+
16-bit External Bus
set mem/byte 0x7fd
=
0x5
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
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MB91FV310APFV-ES 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Proprietary 32-bit Microcontroller CMOS
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