參數資料
型號： MB91F467MAPMC-GSE2
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP216
封裝： 24 X 24 MM, 1.70 MM HEIGHT, 0.40 MM PITCH, LEAD FREE, PLASTIC, QFP-216
文件頁數： 49/128頁
文件大?。?/td> 3125K
代理商： MB91F467MAPMC-GSE2
MB91460M Series
DS07-16613-2E
27
Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception
handling described below may result in execution breaking in an interrupt handling routine or the displayed values
of the flags in the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/
DIV0S instruction:
- a user interrupt is accepted;
- single-step execution is performed;
- or execution breaks due to a data event or from the emulator menu.
1 D0 and D1 flags are updated in advance.
2 An EIT handling routine (user interrupt or emulator) is executed.
3 Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated
to the same values as those in 1).
The following behavior occurs when an ORCCR, STILM, MOV Ri or PS instruction is executed to enable a
user interrupt while that interrupt is in the active state.
4 The PS register is updated in advance.
5 An EIT handling routine (user interrupt) is executed.
6 Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same
value as in 4.
Watchdog timer
The watchdog timer built in this model monitors a program and resets the CPU if the reset defer function is not
executed within a certain period of time or the program runs out of control. Once the function of the watchdog
timer is enabled, the watchdog timer keeps on operating program until it resets the CPU.
As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
executing the program. For those conditions to which this exception applies, see “Chapter 20 Watch dog timer
in Hardware manual”.
Frequency fluctuation
This chip which contains PLL can switch divide-by-two external clock to PLL output fast clock. The clock gear
function which is built in this model prevents consumption power from increasing rapidly at this time.
Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore,
design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an error.
If an error is detected, retransmit the data.
相關PDF資料
PDF描述
MB91F467MAPMC-GSE1 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP216
MB91F467TAPMC-GSE2 RISC MICROCONTROLLER, PQFP144
MB91F469GBPB-GSE1 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320
MB91F469GAPB-GS 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320
MB91F469GBPB-GS 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320
相關代理商/技術參數
參數描述
MB91F467PAPMC-GSE2 制造商:FUJITSU 功能描述:
MB91F467R 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller
MB91F467RCPMC-GE1 制造商:FUJITSU 功能描述:
MB91F467RCPMC-GSE1 制造商:FUJITSU 功能描述:
MB91F467RDPMC-ESE2 制造商:FUJITSU 功能描述:
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