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參數(shù)資料
| 型號： | MB91F155PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 90/103頁 |
| 文件大?。?/td> | 866K |
| 代理商： | MB91F155PFV-G |
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MB91F155/MB91154
87
5.
AC Characteristics
(1) Clock Timing Ratings
(VCC
= 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
*1 : Frequency regulation is the maximum fluctuation from a set center frequency, represented in percentage, when
locked to a multiple.
*2 : The target analog section is the A/D.
*3 : The maximum external bus operating frequency allowed is 25 MHz.
*4 : The value when a minimum clock frequency of 10 MHz is input to X0 and half a division of the oscillator circuit
and the 1/8 gear are in use.
Parameter
Sym-
bol
Pin
name
Condition
Value
Unit
Remarks
Min.
Max.
Clock frequency
(high speed and self oscilla-
tion)
fC
X0, X1
10
16.5
MHz
Range in which self
oscillation is allowed
Clock frequency
(high speed and PLL in use)
Range in which self
oscillation and the
use of the PLL for ex-
ternal clock input are
allowed
Clock frequency
(High speed an 1/2 division
input)
10
18
MHz
Range in which exter-
nal clocks can be in-
put
Clock frequency
(for the calendar macro)
fCA
X0A,
X1A
32
kHz
Self oscillation and
external clocks
Clock cycle time
tC
30.3
1600*4
ns
Frequency regulation *1
(When the PLL is locked.)
f
10
%
Internal operat-
ing clock fre-
quency
CPU
system
fCP
One wait is
set with the
wait con-
troller.
0.625*4
33
MHz
Bus
system
fCPB
0.625*4
25*3
Peripheral
system
fCPP
0.625*4
33
Analog section ex-
cluded. *2
1
33
Analog section *2
Internal operat-
ing clock cycle
time
CPU
system
tCP
30.3
1600*4
ns
Bus
system
tCPB
40*3
1600*4
Peripheral
system
tCPP
30.3
1600*4
Analog section ex-
cluded. *2
30.3
1000
section *2
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