參數(shù)資料
型號(hào)： MB91F155PFV-G
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝： PLASTIC, LQFP-144
文件頁數(shù)： 57/103頁
文件大?。?/td> 866K
代理商： MB91F155PFV-G
MB91F155/MB91154
57
8.
Interrupt Controller
The interrupt controller accepts and arbitrates interrupts.
Block Diagram
to LEVEL0*4
IM
NMI processing
Level
determination
Vector
determination
Level
vector
generation
Priority determination
INT0*2
OR
NMI*6
.
RI00
RI47
(DLYIRQ)
.
DLYI*1
.
ICR00
ICR47
4
5
Request to
withdraw
HLDREQ
6
R bus
6
LEVEL4
HLDCAN*3
to VCT0*5
VCT5
*1 : DLY1 represents the delay interrupt module (delay interrupt generator) . (For detailed information, see
section 10, “Delay Interrupt Module.”
*2 : INT0 is a wake-up signal for the clock controller in sleep or stop mode.
*3 : HLDCAN is a bus surrender request signal for bus masters except for the CPU.
*4 : LEVEL 4 - 0 are interrupt level outputs.
*5 : VCT 5 - 0 are interrupt vector outputs.
*6 : This product type does not have the NMI function.
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