參數(shù)資料
型號: MB91F155APFV-G
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 68/108頁
文件大?。?/td> 2523K
代理商: MB91F155APFV-G
MB91350A Series
62
DS07-16503-5E
2.
External Interrupt/NMI Control
(1) Description
The external interrupt control unit is the block that controls external interrupt requests input to NMI and INT0 to
INT15. The level that is detected as a request can be selected from “H”, “L”, rising edge, or falling edge (except
for NMI).
Note : The MB91F353A/353A/352A/351A does not have INT8 to INT15.
(2) Register list
(3) Block diagram
External interrupt enable register (ENIR)
External interrupt request register (EIRR)
Request level setting register (ELVR)
The above registers (for 8 channels) are available in 2 sets; there are a total of 16 channels.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EN6
EN7
EN5
EN4
EN3
EN2
EN1
EN0
ER6
ER7
ER5
ER4
ER3
ER2
ER1
ER0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
LA7
LB7
LB6
LA6
LB5
LA5
LB4
LA4
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
LA3
LB3
LB2
LA2
LB1
LA1
LB0
LA0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
17
INT0 to INT15
NMI
8
16
R-bus
Interrupt
request
Interrupt enable register
Gate
Request F/F
Edge detection circuit
Interrupt source register
Interrupt level setting register
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