參數(shù)資料
型號： MB91340PMT
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 66 MHz, RISC MICROCONTROLLER, PQFP176
封裝： PLASTIC, LQFP-176
文件頁數(shù)： 69/126頁
文件大?。?/td> 1501K
代理商： MB91340PMT
MB91340/MB91V340
47
s PERIPHERAL RESOURCES
This section describes the location of each peripheral resource register in the memory space.
1.
External Bus Interface Controller
The external bus interface controller controls the interface between the LSI’s internal bus and external memory
and I/O devices.
External Bus Interface Controller Features
Maximum output address width = 32-bit (4GB memory space)
Various different types of external memory (8-bit, 16-bit, or 32-bit devices) can be directly connected and the
controller can support multiple devices with different access timings.
Asynchronous SRAM, asynchronous ROM/FLASH memory (supports multiple write strobe access or byte-
enable access)
Page mode ROM/FLASH memory (2, 4, or 8 page size)
Burst mode ROM/FLASH memory (MBM29BL160D/161D/162D or equivalent)
Address/data multiplexed bus (8-bit or 16-bit width only)
Synchronous memory (ASIC internal memory, etc.)
Note:
Synchronous SRAM cannot be directly connected.
Memory can be divided into eight independent banks (chip select areas) with a separate chip select output
for each bank.
The size of each area can be set in 64Kbyte increments (the size of each chip select area can range from
64Kbyte to 2Gbyte)
Each area can be located anywhere in the physical address space (subject to boundary limitations based on
the area size)
The following functions can be set independently for each chip select area :
Chip select area enable/disable (Access is not performed to disabled areas)
Access timing type settings to suit the type of memory used
Detailed access timing settings (wait cycles and similar settings for each access type)
Data bus width (8-bit, 16-bit, 32-bit)
Byte-ordering setting (big or little endian)
Note:
The CS0 area must be big endian.
Write-prohibit setting (read-only areas)
Enable or disable loading into internal cache
Enable or disable prefetch function
Maximum burst length setting (1, 2, 4, 8)
Different detailed timing settings can be set for each timing type
Even for the same type, different settings can be used for each chip select area.
Up to 15 auto-wait cycles can be specified. (For asynchronous SRAM, ROM, Flash, and I/O areas)
The bus cycle can be extended by the external RDY input. (For asynchronous SRAM, ROM, Flash, and I/O
areas)
Fast access wait and page wait settings are supported (For burst/page mode ROM and Flash areas)
Idle cycles, recovery cycles, setup delays, and similar can be inserted.
DMA supports fly-by transfer
Transfer between memory and I/O can be performed by a single access.
Memory wait cycles can be synchronized with the I/O wait period during fly-by transfer.
Hold times can be maintained by extending access to the data source only.
Separate idle and recovery cycle settings can be specified for use in fly-by transfer.
Supports external bus arbitration using BRQ and BGRNT.
Pins not used by the external interface can be set as general purpose I/O ports.
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