參數(shù)資料
型號： MB91267APMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LFQFP-64
文件頁數(shù)： 36/56頁
文件大?。?/td> 473K
代理商： MB91267APMC
MB91265A Series
41
5.
AC Characteristics
(1) Clock Timing Ratings
(VCC
= 4.0 V to 5.5 V, VSS = AVSS = 0 V)
*1 : The values assume a gear cycle of 1/16.
*2 : When the PLL is used, the lower-limit frequency of the input clock to the X0 and X1 pins determines depending
on the PLL multiplication.
At
× 1 multiplication : more than 8 MHz
At
× 2 to × 8 multiplication : more than 4 MHz
Conditions for measuring the clock timing ratings
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Clock frequency
fC
X0
X1
3.6*2
12
MHz
For using the PLL
within the self-oscilla-
tion enabled range,
set the multiplier for
the internal clock not
to let the operating fre-
quency exceed
33 MHz.
Clock cycle time
tC
X0
X1
83.3
278*2
ns
Input clock pulse
width
PWH
PWL
X0
100
ns
The standard of the
duty ratio is 40
% to 60
%.
Input clock
rising, falling time
tCF
tCR
X0
5
ns
At external clock
Internal operating
clock frequency
fCP
When 4.125 MHz is
input as the X0
clock frequency and
×8 multiplication is
set for the PLL of
the oscillator circuit.
2.06*1
33
MHz CPU
fCPP
2.06*1
33
MHz Peripheral
Internal operating
clock cycle time
tCP
30.3
485*1
ns
CPU
tCPP
30.3
485*1
ns
Peripheral
0.8 VCC
0.2 VCC
tCF
tCR
tC
PWH
PWL
C
= 50 pF
Output pin
X0,
X1
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