參數(shù)資料
型號(hào): MB91110PMT2
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁(yè)數(shù): 67/98頁(yè)
文件大小: 1049K
代理商: MB91110PMT2
MB91110 Series
7
(Continued)
Pin no.
Pin name
I/O*
Circuit type
Function
50
BRQ/P82
I/O
C
This is the external bus open request input. “1” is input if the
external bus is to be opened. It can be used as a port when
not otherwise used.
51
RD
O
G
This is the external bus read strobe.
52
WR0
O
G
This is the external bus write strobe.
53
WR1/P85
I/O
H
55
CS0
O
G
Chip select 0 output (Low active)
56
57
58
59
60
CS1/PA1
CS2/PA2
CS3/PA3
CS4/PA4
CS5/PA5
I/O
H
Chip select 1 output (Low active)
Chip select 2 output (Low active)
Chip select 3 output (Low active)
Chip select 4 output (Low active)
Chip select 5 output (Low active)
They can be used as ports when not otherwise used.
61
CLK/PA6
I/O
H
This is the system clock output. The same clock as the stan-
dard clock is output. This can be used as a port when not oth-
erwise used.
62
63
64
65
68
69
70
71
RAS0/PB0
CS0L/PB1
CS0H/PB2
DW0/PB3
RAS1/PB4
CS1L/PB5
CS1H/PB6
DW1/PB7
I/O
H
RAS output with DRAM bank 0.
CASL output with DRAM bank 0.
CASH output with DRAM bank 0.
WE output with DRAM bank 0. (Low active)
RAS output with DRAM bank 1.
CASL output with DRAM bank 1.
CASH output with DRAM bank 1.
WE output with DRAM bank 1. (Low active)
They can be used as ports when not otherwise used.
72
NMI
I
E
Non Maskable Interrupt (NMI) input. (Low active)
73
74
75
MD0
MD1
MD2
II
These are mode pins from 0 to 2.
Basic MCU operation modes are set using these pins.
They should be connected directly to VCC or VSS for use.
77
78
X0
X1
I
O
A
Clock (oscillation) input.
Clock (oscillation) output.
80
RST
I
B
This is the external reset input. (Low active)
81
HST
I
E
This is the hardware standby input. (Low active)
83
(OPEN)
Set this to OPEN.
84
85
86
(OPEN)
Set this to OPEN.
16-bit bus width
8-bit bus width
D31-24
WR0
D23-16
WR1
(Port is possible)
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