參數資料
型號: MB91110PMT2
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數: 35/98頁
文件大?。?/td> 1049K
代理商: MB91110PMT2
MB91110 Series
40
7.
Bus Interface Outline
The bus interface controls the interface with external memory and external I/O.
Bus Interface Characteristics
24-bit (16 MB) address output
6 individual banks using chip selection function
Random positional setting is possible on the logical address space at minimum 64-KB units.
Total 16 MB
× 6 areas can be set using the address pin and chip selection pin.
16/8-bit bus width can be set per chip selection area.
Insertion of programmable “automatic memory wait” (maximum of 7 cycles)
Supports DRAM interface
3 types of DRAM interface
Double CAS DRAM (Normal DRAM I/F)
Single CAS DRAM
Hyper DRAM
2-bank individual control (control signal i.e. RAS and CAS)
DRAM can be selected from 2CAS/1WE or 1CAS/2WE.
Supports high-speed page mode
Supports CBR / self refresh
Programmable corrugation
Unused addresses / data pins can be used as I/O ports.
Supports “l(fā)ittle endian” mode
Using clock doubler : Internal 50 MHz, external bus 25 MHz operation
Chip Selection Area
A total of six types of chip selection areas are prepared for the bus interface. The position of each area can be
randomly arranged per 64 KB at least using area selection registers (ASR1 to 5) and area mask registers (AMR1
to 5) in an area of 4 GB. In the event that access to an external bus is attempted in areas that are specified by
those registers, the supported chip selection signals (CS0 to CS5) become activated to “L”. Such pins other
than CS0 are deactivated to “H” when reset.
Note : The area 0 is allocated to space outside the area specified by ASR1 to ASR5. External areas other than
0001 0000H to 0005 FFFFH are deemed area 0 on resetting.
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