參數(shù)資料
型號(hào)： MB90V595GCR
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 16 MHz, MICROCONTROLLER, CPGA256
封裝： CERAMIC, PGA-256
文件頁(yè)數(shù)： 17/47頁(yè)
文件大?。?/td> 674K
代理商： MB90V595GCR
MB90595/595G Series
24
s
s CAN CONTROLLER
The CAN controller has the following features:
Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
Supports transmission of data frames by receiving remote frames
16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as 1D acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz)
List of Control Registers
(Continued)
Address
Register
Abbreviation
Access
Initial Value
000080H
Message buffer valid register
BVALR
R/W
00000000 00000000B
000081H
000082H
Transmit request register
TREQR
R/W
00000000 00000000B
000083H
000084H
Transmit cancel register
TCANR
W
00000000 00000000B
000085H
000086H
Transmit complete register
TCR
R/W
00000000 00000000B
000087H
000088H
Receive complete register
RCR
R/W
00000000 00000000B
000089H
00008AH
Remote request receiving register
RRTRR
R/W
00000000 00000000B
00008BH
00008CH
Receive overrun register
ROVRR
R/W
00000000 00000000B
00008DH
00008EH
Receive interrupt enable register
RIER
R/W
00000000 00000000B
00008FH
001B00H
Control status register
CSR
R/W, R
00---000 0----0-1B
001B01H
001B02H
Last event indicator register
LEIR
R/W
-------- 000-0000B
001B03H
001B04H
Receive/transmit error counter
RTEC
R
00000000 00000000B
001B05H
001B06H
Bit timing register
BTR
R/W
-1111111 11111111B
001B07H
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