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MB90595/595G Series
12
I
HANDLING DEVICES
(1) Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up).
In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding V
CC
or an voltage below V
SS
is
applied to input or output pins or a voltage exceeding the rating is applied across V
CC
and V
SS
.
When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal
break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating.
In turning on/turning off the analog power supply, make sure the analog power voltage (AV
CC
, AVRH, DV
CC
) and
analog input voltages not exceed the digital voltage (V
CC
).
(2) Treatment of Unused Pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused
input pins should be pulled up or pulled down through at least 2 k
resistance.
Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
(3) Using external clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
(4) Power supply pins (Vcc/Vss)
In products with multiple V
cc
or V
ss
pins, pins with the same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a
ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating (See the figure below.)
Make sure to connect V
cc
and V
ss
pins via lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1
μ
F between V
cc
and V
ss
pins near the device.
X0
X1
MB90595/595G Series
Using external clock
Open
Vcc
Vss
Vss
Vcc
Vss
Vcc
MB90595/595G
Series
Vcc
Vss
Vcc
Vss