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參數(shù)資料
| 型號： | MB90V540G |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 46/56頁 |
| 文件大?。?/td> | 757K |
| 代理商： | MB90V540G |
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MB90540/545 Series
46
(8) Hold Timing
(V
CC
=
4.5 V to 5.5 V, V
SS
=
0 V, T
A
=
40
°
C to
+
85
°
C)
Value
Note: There is more than 1 cycle from the time HRQ is read to the time the HAK is changed.
(9) UART0/1, Serial I/O Timing
(V
CC
=
4.5 V to 5.5 V, V
SS
=
0 V, T
A
=
–40
°
C to
+
85
°
C)
Value
Note: 1.AC characteristic in CLK synchronized mode.
2.C
L
is load capacity value of pins when testing.
3.t
CP
is the machine cycle (Unit: ns).
Parameter
Symbol
Pin
Condition
Units
Remarks
Min.
Max.
Pin floating
HAK
↓
time
HAK
↑
time
Pin valid time
t
XHAL
HAK
—
30
t
CP
ns
t
HAHV
HAK
t
CP
2 t
CP
ns
Parameter
Symbol
Pin Symbol
Condition
Units Remarks
Min.
Max.
Serial clock cycle time
t
SCYC
SCK0 to SCK2
Internal clock opera-
tion output pins are
C
L
= 80 pF + 1 TTL.
8 t
CP
—
ns
SCK
↓
SOT delay time
t
SLOV
SCK0 to SCK2,
SOT0 to SOT2
–80
80
ns
Valid SIN
SCK
↑
t
IVSH
SCK0 to SCK2,
SIN0 to SIN2
100
—
ns
SCK
↑
Valid SIN hold time
t
SHIX
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
Serial clock "H" pulse width
t
SHSL
SCK0 to SCK2
External clock oper-
ation output pins are
C
L
= 80 pF + 1 TTL.
4 t
CP
—
ns
Serial clock "L" pulse width
t
SLSH
SCK0 to SCK2
4 t
CP
—
ns
SCK
↓
SOT delay time
t
SLOV
SCK0 to SCK2,
SOT0 to SOT2
—
150
ns
Valid SIN
SCK
↑
t
IVSH
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
SCK
↑
Valid SIN hold time
t
SHIX
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
HAK
Each pin
High impedance
t
HAHV
t
XHAL
0.8 V
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
Hold Timing
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