參數(shù)資料
型號(hào)： MB90V540G
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專(zhuān)有
文件頁(yè)數(shù)： 22/56頁(yè)
文件大?。?/td> 757K
代理商： MB90V540G
MB90540/545 Series
22
(Continued)
Address
Register
Abbreviation Access
Peripheral
Initial value
47
H
to 4B
H
Reserved
4C
H
Input capture control status register 0/1
ICS01
R/W
Input Capture 0/1 0 0 0 0 0 0 0 0
B
4D
H
Input capture control status register 2/3
ICS23
R/W
Input Capture 2/3 0 0 0 0 0 0 0 0
B
4E
H
Input capture control status register 4/5
ICS45
R/W
Input Capture 4/5 0 0 0 0 0 0 0 0
B
4F
H
Input capture control status register 6/7
ICS67
R/W
Input Capture 6/7 0 0 0 0 0 0 0 0
B
50
H
Timer control status register 0
TMCSR0
R/W
16-bit Reload
Timer 0
0 0 0 0 0 0 0 0
B
51
H
Timer control status register 0
TMCSR0
R/W
_ _ _ _ 0 0 0 0
B
52
H
Timer register 0/reload register 0
TMR0/
TMRLR0
R/W
XXXXXXXX
B
53
H
Timer register 0/reload register 0
TMR0/
TMRLR0
R/W
XXXXXXXX
B
54
H
Timer control status register 1
TMCSR1
R/W
16-bit Reload
Timer 1
0 0 0 0 0 0 0 0
B
55
H
Timer control status register 1
TMCSR1
R/W
_ _ _ _ 0 0 0 0
B
56
H
Timer register 1/reload register 1
TMR1/
TMRLR1
R/W
XXXXXXXX
B
57
H
Timer register 1/reload register 1
TMR1/
TMRLR1
R/W
XXXXXXXX
B
58
H
Output compare control status register 0
OCS0
R/W
Output Compare
0/1
0 0 0 0 _ _ 0 0
B
59
H
Output compare control status register 1
OCS1
R/W
_ _ _0 0 0 0 0
B
5A
H
Output compare control status register 2
OCS2
R/W
Output Compare
2/3
0 0 0 0 _ _ 0 0
B
5B
H
Output compare control status register 3
OCS3
R/W
_ _ _ 0 0 0 0 0
B
5C
H
to 6B
H
Reserved
6C
H
Timer Data register
TCDT
R/W
I/O Timer
0 0 0 0 0 0 0 0
B
6D
H
Timer Data register
TCDT
R/W
0 0 0 0 0 0 0 0
B
6E
H
Timer Control register
TCCS
R/W
0 0 0 0 0 0 0 0
B
6F
H
ROM mirror register
ROMM
R/W
ROM Mirror
_ _ _ _ _ _ _ 1
B
70
H
to 7F
H
Reserved for CAN 0 Interface. Refer to “CAN Controller Hardware Manual”
80
H
to 8F
H
Reserved for CAN 1 Interface. Refer to “CAN Controller Hardware Manual”
90
H
to 9D
H
Reserved
9E
H
ROM correction control status register
PACSR
R/W
ROM Correction
0 0 0 0 0 0 0 0
B
9F
H
Delayed interrupt/release register
DIRR
R/W
Delayed Interrupt _ _ _ _ _ _ _ 0
B
A0
H
Low-power mode register
LPMCR
R/W
Low Power
Controller
0 0 0 1 1 0 0 0
B
A1
H
Clock selector register
CKSCR
R/W
Low Power
Controller
1 1 1 1 1 1 0 0
B
A2
H
to A4
H
Reserved
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