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參數(shù)資料
| 型號(hào)： | MB90V520A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 38/99頁 |
| 文件大?。?/td> | 978K |
| 代理商： | MB90V520A |
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MB90520A/520B Series
38
3.
Watchdog Timer
The watchdog timer is a timer/counter used to detect faults such as program runaway.
The watchdog timer is a 2-bit counter that counts the clock signal from the timebase timer or clock timer.
Once started, the watchdog timer must be cleared before the 2-bit counter overflows. If an overflow occurs,
the CPU is reset.
Interval time for the watchdog timer
HCLK : Oscillation Clock (4 MHz)
* : The difference between the maximum and minimum watchdog timer interval times is due to the timing when the
counter is cleared.
* : As the watchdog timer is a 2-bit counter that counts the carry-up signal from the timebase timer or clock timer,
clearing the timebase timer (when operating on HCLK) or the clock timer (when operating on SCLK) lengthens
the time until the watchdog timer reset is generated.
Watchdog timer count clock
Events that stop the watchdog timer
1 : Stop due to a power-on reset
2 : Reset due to recovery from hardware standby mode
3 : Watchdog reset
Events that clear the watchdog timer
1 : External reset input from the RST pin.
2 : Writing “0” to the software reset bit.
3 : Writing “0” to the watchdog control bit (second and subsequent times) .
4 : Changing to sleep mode (clears the watchdog timer and temporarily halts the count) .
5 : Changing to pseudo-clock mode (clears the watchdog timer and temporarily halts the count) .
6 : Changing to clock mode (clears the watchdog timer and temporarily halts the count) .
7 : Changing to stop mode (clears the watchdog timer and temporarily halts the count) .
SCLK : Sub-Clock (8.192 kHz)
Min
Max
Clock Period
2
14
±
2
11
/
HCLK Approx. 0.438 s Approx. 0.563 s
2
16
±
2
13
/
HCLK Approx. 3.500 s Approx. 4.500 s 2
15
±
2
12
/
SCLK
2
18
±
2
15
/
HCLK Approx. 7.000 s Approx. 9.000 s 2
16
±
2
13
/
SCLK
Min
Max
Clock Period
2
12
±
2
9
/
SCLK
Approx. 3.58 ms
Approx. 4.61 ms
Approx. 14.33 ms
Approx. 18.30 ms
Approx. 57.23 ms
Approx. 458.75 ms Approx. 589.82 ms 2
21
±
2
18
/
HCLK Approx. 14.00 s Approx. 18.00 s 2
17
±
2
14
/
SCLK
Approx. 73.73 ms
WTC : WDCS
HCLK : Oscillation clock
PCLK : PLL clock
SCLK : Sub-clock
“0”
Count the clock timer output.
Count the clock timer output.
“1”
Count the timebase timer output.
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