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| 型號(hào)： | MB90T678PF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 48-CFP -55 to 125 |
| 中文描述： | 16-BIT, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 42/124頁(yè) |
| 文件大小： | 2584K |
| 代理商： | MB90T678PF |
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MB90670/675 Series
42
(3) Output Port
Port 7 is a general-purpose output port having a combined function as an output compare (OCU) output. Note
that only OCU output can be output when the pin is configured as an output, and it is not used for outputting
given data by writing to the data register. Each pin can be switched between an output compare output and a
port bitwise.
Operation as output port (operation of OCU output)
Setting the corresponding bit of the DDR register to “1” configures the pin as an output port. In this case, lower
4-bit of CCR01 and CCR register are output.
When configured as an output, the output buffer is turned on and data retained in the output latch in the PDR
of the output compare is output to the pin.
Writing data to DOT bit of the OCU control register (CCR01, CCR11) corresponding to each pin writes data
in synchronization to a match operation of the output compare and output to the pin.
Reading the PDR register returns the pin level (same as the output latch value of the PDR).
When output of output compare is enabled, an output value from the output compare can be read out.
Operation as input port
Setting corresponding bit of the DDR register to “0” configures the pin as input port.
When the pin is configured as an input port, the output buffer is turned off and the pin is put into a high-
impedance status.
Reading the PDR register returns the pin level (“0” or “1”).
Block diagram
DDR read
OCU control register
OCU control register write
DDR (port direction register)
Direction latch
Standby control (SPL=1)
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
P-ch
N-ch
PDR (port data register)
I
Pin
DDR write
PDR read
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