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參數(shù)資料
| 型號： | MB90T553APF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Quadruple Bus Buffer Gates With 3- State Outputs 14-CDIP -55 to 125 |
| 中文描述： | 16-BIT, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 44/58頁 |
| 文件大小： | 695K |
| 代理商： | MB90T553APF |
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MB90550A/550B Series
44
(13) I
2
C Interface
(V
CC
=
5.0 V
±
10%, V
SS
=
AV
SS
=
0.0 V, T
A
=
40
°
C to +85
°
C)
Value
Notes: “m” and“n” in the above table represent the values of shift clock frequency setting bits (CS4 to CS0) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
t
DOSUO
represents the minimum value when the interrupt period is equal to or greater than the SCL “L” width.
The SDA and SCL output values indicate that that rise time is 0 ns.
Parameter
Symbol
Pin name
Unit
Remarks
Min.
Max.
Internal clock cycle time
t
CP
—
62.5
666
ns
All products
Start condition output
t
STAO
SDA0 to SDA2
SCL0 toSCL2
t
CP
×
m
×
n/2 – 20 t
CP
×
m
×
n/2 + 20
t
CP
(m
×
n/2 + 4)
– 20
ns
Only as master
Stop condition output
t
STOO
t
CP
(m
×
n/2 + 4)
+ 20
ns
Start condition detection
t
STAI
3 t
CP
+ 40
—
ns
Only as slave
Stop condition detection
t
STOI
3 t
CP
+ 40
t
CP
×
m
×
n/2 – 20 t
CP
×
m
×
n/2 + 20
t
CP
(m
×
n/2 + 4)
– 20
—
ns
SCL output “L” width
t
LOWO
SCL0 to SCL2
ns
Only as master
SCL output “H” width
t
HIGHO
t
CP
(m
×
n/2 + 4)
+ 20
ns
SDA output delay time
Setup after SDA output
interrupt period
SCL input “L” width
t
DOO
SDA0 to SDA2
SCL0 to SCL2
2 t
CP
– 20
2 t
CP
+ 20
ns
t
DOSUO
4 t
CP
– 20
—
ns
t
LOWI
SCL0 to SCL2
3 t
CP
+ 40
—
ns
SCL input “H” width
t
HIGHI
t
CP
+ 40
—
ns
SDA input setup time
t
SUI
SDA0 to SDA2
SCL0 to SCL2
40
—
ns
SDA input hold time
t
HOI
0
—
ns
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