參數(shù)資料
型號: MB90P234
廠商: Fujitsu Limited
英文描述: 16-Bit Registered Transceivers With 3-State Outputs 56-CFP -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 47/83頁
文件大?。?/td> 1513K
代理商: MB90P234
47
MB90230 Series
13. Delay Interruupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module
allows an interrupt request to the F
2
MC-16F CPU to be generated or canceled by software.
(1) Register Configuration
(2) Block Diagram
14.
Clock Output Control Register
The clock output control register outputs the output from the communication prescaler to the pin.
(1) Register Configuration
R0
15
14
13
12
11
10
9
8
Address: 00009F
H
Read/write
Initial value
DIRR
Delayed interrupt source
generate/release register
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(R/W)
(0)
bit
Interrupt source latch
Delayed interrupt source generate/release decoder
F
2
M
CKEN
FRQ1
FRQ0
15
14
13
12
11
10
9
8
Address: 00002E
H
CLKR
Read/write
Initial value
Clock control register
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
bit
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