95
MB90210 Series
Table 26
Multiple Data Transfer Instructions [18 Instruction]
*1: 256 when 5 + imm8
× 5, imm8 is 0.
*2: 256 when 5 + imm8
× 5 + (a), imm8 is 0.
*3: (Number of transfer cycles)
× (b) × 2
*4: (Number of transfer cycles)
× (c) × 2
*5: The bank register specified by bnk is the same as that for the MOVS instruction.
Mnemonic
#
~
B
Operation
LH AH
IS
T
N
Z
V
C RMW
MOVM @A, @RLi, #imm8
3
*1
*3 Multiple data transfer
byte ((A))
← ((RLi))
–
––––
–
MOVM @A, eam, #imm8
3 +
*2
*3 Multiple data transfer
byte ((A))
← (eam)
–
––––
–
MOVM addr16, @RLi, #imm8
5
*1
*3 Multiple data transfer
byte (addr16)
← ((RLi))
–
––––
–
MOVM addr16, @eam, #imm8 5 +
*2
*3 Multiple data transfer
byte (addr16)
← (eam)
–
––––
–
MOVMW
@A, @RLi, #imm8
3
*1
*4 Multiple data transfer
word ((A))
← ((RLi))
–
––––
–
MOVMW
@A, eam, #imm8
3 +
*2
*4 Multiple data transfer
word ((A))
← (eam)
–
––––
–
MOVMWaddr16, @RLi, #imm8
5
*1
*4 Multiple data transfer
word (addr16)
← ((RLi))
–
––––
–
MOVMWaddr16, @eam, #imm8
5 +
*2
*4 Multiple data transfer
word (addr16)
← (eam)
–
––––
–
MOVM @RLi, @A, #imm8
3
*1
*3 Multiple data transfer
byte ((RLi))
← ((A))
–
––––
–
MOVM @eam, A, #imm8
3 +
*2
*3 Multiple data transfer
byte (eam)
← ((A))
–
––––
–
MOVM @RLi, addr16, #imm8
5
*1
*3 Multiple data transfer
byte ((RLi))
← (addr16)
–
––––
–
MOVM @eam, addr16, #imm8 5 +
*2
*3 Multiple data transfer
byte (eam)
← (addr16)
–
––––
–
MOVMW
@RLi, @A, #imm8
3
*1
*4 Multiple data transfer
word ((RLi))
← ((A))
–
––––
–
MOVMW
@eam, A, #imm8
3 +
*2
*4 Multiple data transfer
word (eam)
← ((A))
–
––––
–
MOVMW@RLi, addr16, #imm8
5
*1
*4 Multiple data transfer
word ((RLi))
← (addr16)
–
––––
–
MOVMW@eam, addr16, #imm8
5 +
*2
*4 Multiple data transfer
word (eam)
← (addr16)
–
––––
–
MOVM bnk: addr16,
bnk: addr16, #imm8
*5
7
*1
*3 Multiple data transfer
byte (bnk: addr16)
←
(bnk: addr16)
–
––––
–
MOVMW
bnk: addr16,
bnk: addr16, #imm8
*5
7
*1
*4 Multiple data transfer
word (bnk: addr16)
←
(bnk: addr16)
–
––––
–