參數(shù)資料
型號(hào)： MB90P214BPF
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 41/100頁(yè)
文件大?。?/td> 1681K
代理商： MB90P214BPF
45
MB90210 Series
6. PWC(Pulse Width Count) Timer
The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count
function and a reload timer function. The hardware configuration of this module is a 16-bit up-count timer, an
input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. Using
these components, the PWC timer provides the following features:
Timer functions:
An interrupt request can be generated at set time intervals.
Pulse signals synchronized with the timer cycle can be output.
The reference internal clock can be selected from among three internal clocks.
Pulse-width count functions:
The time between arbitrary pulse input events can be counted.
The reference internal clock can be selected from among three internal clocks.
Various count modes:
“H” pulse width (
↑ to ↓) /“L” pulse width (↑ to ↓)
Rising-edge cycle (
↑ to ↑) /Falling-edge cycle (↓ to ↓)
Count between edges (
↑ or ↓ to ↓ or ↑)
Cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input
pulse, with an 8 bit input divider.
An interrupt request can be generated once counting has been performed.
The number of times counting is to be performed (once or subsequently) can
be selected.
The MB90210 series contains four channels for the PWC timer.
(1) Register Configuration
PWC control status register (PWCSR)
000071 H
000075H
000079H
00007DH
ch.0
ch.1
ch.2
ch.3
Address:
PWC control status register (Upper byte)
000070 H
000074H
000078H
00007CH
ch.0
ch.1
ch.2
ch.3
Address:
PWC control status register (Lower byte)
15
14
13
12
11
10
9
8
7654
3210
Bit
CKS1
MOD0
MOD1
MOD2
S/C
PIS0
PIS1
CKS0
STRT
POUT
ERR
OVIE
OVIR
EDIE
EDIR
STOP
PWCSRx
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/write
Initial value
Read/write
Initial value
→
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